公开(公告)号：US20170025270A1

公开(公告)日：2017-01-26

申请号：US14807289

申请日：2015-07-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Shesh Mani PANDEY

IPC: H01L21/02 ,  H01L21/308 ,  H01L27/08 ,  H01L21/283 ,  H01L49/02 ,  H01L21/3065 ,  H01L21/3105

CPC classification number: H01L23/5223 ,  H01L21/02186 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31051 ,  H01L23/53228 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.

Abstract translation: 一种方法可以包括在半导体结构上施加图案化掩模，所述半导体结构具有电介质层，使用所述图案化掩模形成在所述电介质层中形成的第一和第二间隔开的金属结构之间的材料形成沟槽，以及设置电介质材料形成 在材料形成沟槽中。

公开(公告)号：US20160049327A1

公开(公告)日：2016-02-18

申请号：US14459444

申请日：2014-08-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil Kumar SINGH ,  Ravi Prakash SRIVASTAVA ,  Teck Jung TANG ,  Mark Alexander ZALESKI

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76825 ,  H01L2221/1047

Abstract: Methods are provided for fabricating an interlayer structure useful in, for instance, providing BEOL interconnect for circuit structures. The method includes, for instance, providing an interlayer structure, including: providing an uncured insulating layer above a substrate structure; forming an energy removal film over the uncured insulated layer; forming at least one opening through the energy removal film and extending at least partially into the uncured insulating layer; and applying energy to cure the uncured insulating layer, establishing a cured insulating layer, and decomposing in part the energy removal film, establishing a reduced thickness, energy removal film over the cured insulating layer, the interlayer structure including the cured insulating layer, and the applying energy decreasing an aspect ratio(s) of the one opening(s). In one implementation, the uncured insulating layer includes porogens which also decompose partially during applying energy to further improve the aspect ratio(s).

Abstract translation: 提供了用于制造用于例如为电路结构提供BEOL互连的层间结构的方法。 该方法包括例如提供层间结构，包括：在衬底结构之上提供未固化的绝缘层; 在未固化的绝缘层上形成能量去除膜; 通过所述能量去除膜形成至少一个开口并且至少部分地延伸到所述未固化的绝缘层中; 并施加能量以固化未固化绝缘层，建立固化绝缘层，并部分分解能量去除膜，在固化绝缘层上形成厚度减小的能量去除膜，包括固化绝缘层的层间结构，以及 施加减小一个开口的纵横比的能量。 在一个实施方案中，未固化的绝缘层包括在施加能量的同时分解部分以进一步改善纵横比的致孔剂。

公开(公告)号：US20170047290A1

公开(公告)日：2017-02-16

申请号：US14824181

申请日：2015-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil Kumar SINGH ,  Ravi Prakash SRIVASTAVA ,  Nicholas Robert STOKES

IPC: H01L23/535 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/2885 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/7684 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76873 ,  H01L21/76883 ,  H01L21/76895 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/535

Abstract: Metal filling processes for semiconductor devices and methods of fabricating semiconductor devices. One method includes, for instance: obtaining a wafer with at least one contact opening; depositing a metal alloy into at least a portion of the at least one contact opening; separating the metal alloy into a first metal layer and a second metal layer; depositing a barrier stack over the wafer; forming at least one trench opening; forming at least one via opening; and depositing at least one metal material into the trench openings and via openings. An intermediate semiconductor device is also disclosed.

Abstract translation: 用于半导体器件的金属填充工艺和制造半导体器件的方法。 一种方法包括例如：获得具有至少一个接触开口的晶片; 将金属合金沉积到所述至少一个接触开口的至少一部分中; 将金属合金分离成第一金属层和第二金属层; 在晶片上沉积势垒堆叠; 形成至少一个沟槽开口; 形成至少一个通孔; 以及将至少一种金属材料沉积到沟槽开口和通孔中。 还公开了一种中间半导体器件。

公开(公告)号：US20190371736A1

公开(公告)日：2019-12-05

申请号：US16000174

申请日：2018-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sunil Kumar SINGH ,  Shesh Mani PANDEY

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to interconnect structures with reduced capacitance and methods of manufacture. The method includes: forming one or more lower metal lines in a dielectric material; forming an airgap structure in an upper dielectric material above the one or more lower metal lines, by subjecting material to a curing process; and forming an upper metal structure above the airgap structure.

公开(公告)号：US20190318955A1

公开(公告)日：2019-10-17

申请号：US15950907

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jin WALLNER ,  Katherina BABICH ,  Sunil Kumar SINGH

IPC: H01L21/762 ,  H01L29/66 ,  H01L29/06

Abstract: A method of forming an SDB that is self-aligned to a dummy gate and the resulting device are provided. Embodiments include providing a plurality of gates over a SOI layer above a BOX layer, each gate having a pair of sidewall spacers and a cap layer, and a raised S/D epitaxial regions over the SOI layer between each gate; removing a gate of the plurality of gates and a portion of the SOI layer exposed by the removing of the gate, and a portion of the BOX layer underneath the SOI layer, the removing forms a trench; forming a liner of a first dielectric material over and along sidewalls of the trench; and filling the trench with a second dielectric material.

公开(公告)号：US20170178953A1

公开(公告)日：2017-06-22

申请号：US14978650

申请日：2015-12-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Sohan Singh MEHTA ,  Ravi Prakash SRIVASTAVA

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/76817 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76814 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/528

Abstract: Back end of line via formation for semiconductor devices and methods of fabricating the semiconductor devices. One method includes, for instance: obtaining a wafer with a substrate and at least one contact in the substrate; depositing at least one lithography stack over the substrate; performing lithography to pattern at least one via opening; depositing a block co-polymer coating over the wafer into the at least one via opening; performing an ashing to remove excess block co-polymer material and form block co-polymer caps; and performing a thermal bake to separate the block co-polymer caps into a first material and a second material. An intermediate semiconductor device is also disclosed.

公开(公告)号：US20160336264A1

公开(公告)日：2016-11-17

申请号：US14711380

申请日：2015-05-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jonathan Lee RULLAN ,  Sunil Kumar SINGH

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532 ,  H01L21/288 ,  H01L23/522 ,  H01L21/033 ,  H01L21/3105

CPC classification number: H01L21/76847 ,  H01L21/0276 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76811 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76895 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L23/535

Abstract: A methodology enabling filling of high aspect ratio cavities, with no voids or gaps, in an IC device and the resulting device are disclosed. Embodiments include providing active area and/or gate contacts in a first ILD; forming selective protective caps on upper surfaces of the contacts; forming a second ILD on upper surfaces of the protective caps and on an upper surface of the first ILD; forming a hard-mask stack on the second ILD; forming, in the second ILD and hard-mask stack, cavities exposing one or more protective caps; removing selective layers in the stack to decrease depths of the cavities; and filling the cavities with a metal layer, wherein the metal layer in one or more cavities connects to an upper surface of the one or more exposed protective caps.

Abstract translation: 公开了一种能够填充IC器件和所得器件中无空隙或间隙的高纵横比腔的方法。 实施例包括在第一ILD中提供有源区和/或门触点; 在触点的上表面上形成选择性保护帽; 在保护盖的上表面和第一ILD的上表面上形成第二ILD; 在第二ILD上形成硬掩模叠层; 在第二ILD和硬掩模叠层中形成暴露一个或多个保护盖的空腔; 去除叠层中的选择层以减小空腔的深度; 以及用金属层填充空腔，其中一个或多个空腔中的金属层连接到一个或多个暴露的保护盖的上表面。

公开(公告)号：US20160190003A1

公开(公告)日：2016-06-30

申请号：US14676633

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH

IPC: H01L21/768 ,  H01L21/3105 ,  H01L21/311 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/31144 ,  H01L21/76813 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of reducing defects in and improving reliability of Back-End-Of-Line (BEOL) metal fill includes providing a starting metallization structure for semiconductor device(s), the metallization structure including a bottom layer of contact(s) surrounded by a dielectric material. The starting metallization structure further includes an etch-stop layer over the bottom layer, a layer of dielectric material over the etch-stop layer, a first layer of hard mask material over the dielectric layer, a layer of work function hard mask material over the first hard mask layer, a second layer of hard mask material over the work function hard mask layer, via(s) to the first hard mask layer and other via(s) into the etch-stop layer. The method further includes protecting the other via(s) while removing the second hard mask layer and the layer of work function hard mask material, and filling the vias with metal. Protecting the other via(s) may include, prior to the removing, filling the other via(s) with an Energy Removal Film (ERF) up to a top surface of the first hard mask layer, and, after the removing, removing the ERF material.

Abstract translation: 一种减少后端在线（BEOL）金属填充物的缺陷并提高其可靠性的方法包括为半导体器件提供起始金属化结构，金属化结构包括由 介电材料。 起始金属化结构还包括在底层上的蚀刻停止层，在蚀刻停止层上方的介电材料层，在电介质层上的第一层硬掩模材料，在第一层上的功函数硬掩模材料 第一硬掩模层，在功函数硬掩模层上的第二层硬掩模材料，经由第一硬掩模层和其它通孔进入蚀刻停止层。 该方法还包括保护另一个通孔，同时移除第二硬掩模层和工作层功能硬掩模材料，并用金属填充通孔。 保护另一个通孔可以包括在去除之前用能量去除膜（ERF）填充另一个通孔直到第一硬掩模层的顶表面，并且在移除之后，移除 ERF材料。

公开(公告)号：US20150076705A1

公开(公告)日：2015-03-19

申请号：US14027479

申请日：2013-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Matthew HERRICK ,  Teck Jung TANG ,  Dewei XU

IPC: H01L23/48 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L23/5226 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76829 ,  H01L21/76835 ,  H01L21/76849 ,  H01L21/76877 ,  H01L23/481 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1047 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interlayer fabrication methods and interlayer structure are provided having reduced dielectric constants. The methods include, for example: providing a first uncured insulating layer with an evaporable material; and disposing a second uncured insulating layer having porogens above the first uncured insulating layer. The interlayer structure includes both the first and second insulating layers, and the methods further include curing the interlayer structure, leaving air gaps in the first insulating layer, and pores in the second insulating layer, where the air gaps are larger than the pores, and where the air gaps and pores reduce the dielectric constant of the interlayer structure.

公开(公告)号：US20170294378A1

公开(公告)日：2017-10-12

申请号：US15625035

申请日：2017-06-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sunil Kumar SINGH ,  Shesh Mani PANDEY

IPC: H01L23/522 ,  H01L49/02 ,  H01L23/532

CPC classification number: H01L23/5223 ,  H01L21/02186 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31051 ,  H01L23/53228 ,  H01L27/0805 ,  H01L28/40 ,  H01L28/55

Abstract: A method can include applying a patterned mask over a semiconductor structure, the semiconductor structure having a dielectric layer, forming using the patterned mask a material formation trench intermediate first and second spaced apart metal formations formed in the dielectric layer, and disposing a dielectric material formation in the material formation trench.