公开(公告)号：US10770344B2

公开(公告)日：2020-09-08

申请号：US16244071

申请日：2019-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yuping Ren ,  Haigou Huang ,  Ravi Prakash Srivastava ,  Zhiguo Sun ,  Qiang Fang ,  Cheng Xu ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/311 ,  H01L21/02

Abstract: A method of fabricating interconnects in a semiconductor device is provided, which includes forming an interconnect layer having a conductive line and depositing a first aluminum-containing layer over the interconnect layer. A dielectric layer is deposited over the first aluminum-containing layer, followed by a second aluminum-containing layer deposited over the dielectric layer. A via opening is formed in the second aluminum-containing layer through to the conductive line, wherein the via opening has chamferless sidewalls.

公开(公告)号：US10446395B1

公开(公告)日：2019-10-15

申请号：US15950364

申请日：2018-04-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaohan Wang ,  Qiang Fang ,  Zhiguo Sun ,  Jinping Liu ,  Hui Zang

IPC: H01L21/033 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528

Abstract: Methods of self-aligned multiple patterning and structures formed by self-aligned multiple patterning. A mandrel line is patterned from a first mandrel layer disposed on a hardmask and a second mandrel layer disposed over the first mandrel layer. A first section of the second mandrel layer of the mandrel line is removed to expose a first section of the first mandrel layer. The first section of the first mandrel layer is masked, and the second sections of the second mandrel layer and the underlying second portions of the first mandrel layer are removed to expose first portions of the hardmask. The first portions of the hardmask are then removed with an etching process to form a trench in the hardmask. A second portion of the hardmask is masked by the first portion of the first mandrel layer during the etching process to form a cut in the trench.

公开(公告)号：US09741610B2

公开(公告)日：2017-08-22

申请号：US14740035

申请日：2015-06-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qiang Fang ,  Zhiguo Sun ,  Jiehui Shu

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L21/311

CPC classification number: H01L21/76879 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7684 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53238

Abstract: A starting metallization structure for electrically coupling one or more underlying semiconductor devices, the structure including a bottom layer of dielectric material with metal-filled via(s) situated therein, a protective layer over the bottom layer, and a top layer of dielectric material over the protective layer. A sacrificial layer of amorphous silicon is formed over the top layer of dielectric material, a protective layer is formed over the sacrificial layer and via(s) through each layer above the metal-filled via(s) to expose the metal of the metal-filled via(s). The protective layer is then selectively removed, as well as the sacrificial layer of amorphous silicon.

公开(公告)号：US10109521B1

公开(公告)日：2018-10-23

申请号：US15606895

申请日：2017-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Qiang Fang ,  Shafaat Ahmed ,  Changhong Wu ,  Zhiguo Sun ,  Jiehui Shu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532

Abstract: A method of forming hybrid Co and Cu CA/CB contacts and the resulting device are provided. Embodiments include forming a forming a plurality of trenches through an ILD down to a substrate; forming a first metal liner on side and bottom surfaces of each trench and over the ILD; annealing the first metal liner; forming a second metal liner over the first metal liner; forming a first plating layer over a portion of the second metal liner in each trench; forming a second plating layer over the second metal liner and first plating layer in a remaining portion of each trench, the first and second plating layers being different materials; and planarizing the second plating layer and the second and first metal liners down to the ILD.

公开(公告)号：US20180012791A1

公开(公告)日：2018-01-11

申请号：US15202867

申请日：2016-07-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhiguo Sun ,  Qiang Fang ,  Suraj K. Patil ,  Jiehui Shu

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/7682 ,  H01L21/76849 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063

Abstract: Interconnect structures and methods of forming such interconnect structures. A spacer is formed inside an opening in a dielectric layer. After the spacer is formed, a conductive plug is formed inside the opening in the dielectric layer. After the conductive plug is formed, the spacer is removed to define an air gap located inside the opening in the dielectric layer. The air gap is located between the conductive plug and the opening in the dielectric layer.

公开(公告)号：US20170287777A1

公开(公告)日：2017-10-05

申请号：US15091138

申请日：2016-04-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Suraj K. Patil ,  Zhiguo Sun ,  Keith Tabakman

IPC: H01L21/768 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/41725 ,  H01L21/285 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76864 ,  H01L21/76897 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/66477

Abstract: One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening.

公开(公告)号：US09502232B2

公开(公告)日：2016-11-22

申请号：US14321866

申请日：2014-07-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sipeng Gu ,  Sandeep Gaan ,  Zhiguo Sun ,  Huang Liu ,  Adam Selsley

IPC: H01L21/02 ,  H01L21/321

CPC classification number: H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/321

Abstract: Methods for fabricating a layered circuit structure are provided, which include, for instance: depositing a first material layer above a substrate, the first material layer having an oxidized upper surface; providing a second material layer over the oxidized upper surface of the first material layer; and inhibiting diffusion of one or more elements from the oxidized upper surface of the first material layer into either the first material layer or the second material layer during the providing of the second material layer over the oxidized upper surface of the first material layer. The inhibiting may include one or more of modifying a characteristic(s) of the first material layer, forming a protective layer over the oxidized upper surface of the first material layer, or altering at least one process parameter employed in providing the second material layer.

Abstract translation: 提供了一种用于制造分层电路结构的方法，其包括例如：在衬底上沉积第一材料层，第一材料层具有氧化的上表面; 在所述第一材料层的氧化的上表面上提供第二材料层; 并且在第二材料层在第一材料层的氧化的上表面上提供第二材料层期间，抑制一个或多个元件从第一材料层的氧化的上表面扩散到第一材料层或第二材料层中。 抑制可以包括一个或多个修饰第一材料层的特征，在第一材料层的氧化的上表面上形成保护层，或改变在提供第二材料层中使用的至少一个工艺参数。

公开(公告)号：US09142422B2

公开(公告)日：2015-09-22

申请号：US14070823

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hung-Wei Liu ,  Zhiguo Sun ,  Huang Liu ,  Jin Ping Liu

IPC: H01L21/311 ,  H01L23/58

CPC classification number: H01L23/564 ,  H01L21/02126 ,  H01L21/02129 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/31155 ,  H01L21/76826 ,  H01L21/76837 ,  H01L21/823418 ,  H01L23/58 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of facilitating fabrication of defect-free semiconductor structures are provided which include, for instance: providing a dielectric layer, the dielectric layer comprising at least one consumable material; selectively removing a portion of the dielectric layer, wherein the selectively removing consumes, in part, a remaining portion of the at least one consumable material, leaving, within the remaining portion of the dielectric layer, a depleted region; and subjecting the depleted region of the dielectric layer to a treatment process, to restore the depleted region with at least one replacement consumable material, thereby facilitating fabrication of a defect-free semiconductor structure.

Abstract translation: 提供了有助于制造无缺陷半导体结构的方法，其包括例如：提供介电层，该电介质层包括至少一种可消耗材料; 选择性地去除所述电介质层的一部分，其中所述选择性去除部分地消耗所述至少一种可消耗材料的剩余部分，在所述电介质层的剩余部分内留下耗尽区; 并且对所述介质层的所述耗尽区进行处理处理，以用至少一种替代的可消耗材料恢复所述耗尽区，从而有助于制造无缺陷的半导体结构。

公开(公告)号：US10714380B2

公开(公告)日：2020-07-14

申请号：US16171477

申请日：2018-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ravi P. Srivastava ,  Sipeng Gu ,  Sunil K. Singh ,  Xinyuan Dou ,  Akshey Sehgal ,  Zhiguo Sun

IPC: H01L21/768 ,  H01L21/02

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to smooth sidewall structures and methods of manufacture. The method includes: forming a plurality of mandrel structures; forming a first spacer material on each of the plurality of mandrel structures; forming a second spacer material over the first spacer material; and removing the first spacer material and the plurality of mandrel structures to form a sidewall structure having a sidewall smoothness greater than the plurality of mandrel structures.

公开(公告)号：US10043753B2

公开(公告)日：2018-08-07

申请号：US15377592

申请日：2016-12-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Huy Cao ,  Zhiguo Sun ,  Joseph F. Shepard, Jr. ,  Moosung M. Chae

IPC: H01L23/522 ,  H01L21/768 ,  H01L21/764 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02271 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76837 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to airgaps which isolate metal lines and methods of manufacture. The structure includes: a plurality of metal lines formed on an insulator layer; and a dielectric material completely filling a space having a first dimension between metal lines of the plurality of metal lines and providing a uniform airgap with a space having a second dimension between metal lines of the plurality of metal lines. The first dimension is larger than the second dimension.