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    PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF
    2.
    发明申请
    PROGRAMMABLE VIA DEVICES WITH METAL/SEMICONDUCTOR VIA LINKS AND FABRICATION METHODS THEREOF 有权

    公开(公告)号：US20170092583A1

    公开(公告)日：2017-03-30

    申请号：US14867341

    申请日：2015-09-28

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ajey P. JACOB ,  Suraj K. PATIL ,  Min-hwa CHI

    IPC: H01L23/525 ,  H01L23/522

    CPC classification number: H01L23/5256 ,  H01L23/5226

    Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

    DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES
    5.
    发明申请
    DUAL-WIDTH FIN STRUCTURE FOR FINFETS DEVICES 审中-公开
    FINFET设备的双宽度结构

    公开(公告)号：US20160027775A1

    公开(公告)日：2016-01-28

    申请号：US14341423

    申请日：2014-07-25

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Murat Kerem AKARVARDAR ,  Ajey P. JACOB ,  Andreas KNORR

    IPC: H01L27/088 ,  H01L29/161 ,  H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16 ,  H01L29/49

    CPC classification number: H01L29/66545 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/16 ,  H01L29/161 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/66795 ,  H01L29/785

    Abstract: A method of forming a FinFET device having Si or high Ge concentration SiGe fins with a narrow width under the gate and a wider width under the spacer and the resulting device are provided. Embodiments include forming fins; forming a dummy gate, with a dummy oxide thereunder and a nitride HM on top, on the fins, the dummy gate formed perpendicular to the fins; forming a nitride spacer on each side of the dummy gate; forming an oxide in-between adjacent gates and planarizing; removing the nitride HM and dummy gate, forming a channel between the nitride spacers; oxidizing the fins in the channel; removing the dummy oxide and oxidized portions of the fins; and forming a RMG on the fins between the nitride spacers.

    Abstract translation: 提供了一种形成具有Si或高Ge浓度SiGe鳍的FinFET器件的方法，该栅极在栅极下方具有窄的宽度，并且在间隔物和形成的器件下形成更宽的宽度。 实施例包括形成翅片; 在翅片上形成虚拟栅极，其上具有虚拟氧化物和顶部​​的氮化物HM，垂直于鳍片形成的虚拟栅极; 在所述虚拟栅极的每一侧上形成氮化物间隔物; 在相邻栅极之间形成氧化物并平坦化; 去除氮化物HM和虚拟栅极，在氮化物间隔物之间​​形成通道; 氧化通道中的翅片; 去除虚拟氧化物和翅片的氧化部分; 并在氮化物间隔物之间​​的翅片上形成RMG。

    NON-PLANAR WAVEGUIDE STRUCTURES
    6.
    发明申请
    NON-PLANAR WAVEGUIDE STRUCTURES 审中-公开

    公开(公告)号：US20190107672A1

    公开(公告)日：2019-04-11

    申请号：US15725524

    申请日：2017-10-05

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Ajey P. JACOB

    IPC: G02B6/122 ,  G02B6/132

    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to non-planar waveguide structures and methods of manufacture. The waveguide structure includes: non-planar structures composed of a first material; a cladding layer over the non-planar structures composed of a second material; and a material formed over the cladding layer.

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