Abstract:
The disclosure relates to integrated circuit (IC) structures with substantially T-shaped wires, and methods of forming the same. An IC structure according to the present disclosure can include a first substantially T-shaped wire including a first portion extending in a first direction, and a second portion extending in a second direction substantially perpendicular to the first direction; an insulator laterally abutting the first substantially T-shaped wire at an end of the first portion, opposite the second portion; and a pair of gates each extending in the first direction and laterally abutting opposing sidewalls of the insulator and the first portion of the substantially T-shaped wire.
Abstract:
The present disclosure relates to semiconductor structures and, more particularly, to contacts for local connections and methods of manufacture. The structure includes: at least one contact electrically shorted to a gate structure and a source/drain contact and located below a first wiring layer; and gate, source and drain contacts extending from selected gate structures and electrically connecting to the first wiring layer.
Abstract:
At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.
Abstract:
At least one method, apparatus and system disclosed involves circuit layout for comprising a unidirectional metal layout. A first trench silicide (TS) formation is formed in a first active area of a functional cell. A first CA formation if formed above the first TS formation. A first vertical metal formation is formed in a first metal layer from the first active area to a second active area of the functional cell. The first vertical metal formation is formed offset relative to, and in contact with, the CA formation. A second TS formation is formed in a second active area of the functional cell. A second CA formation is formed above the second TS formation. The CA formation is formed offset the first vertical metal formation, operatively coupling the first and second active areas.
Abstract:
One method includes forming a mandrel element above a hard mask layer, forming first and second spacers on the mandrel element, removing the mandrel element, a first opening being defined between the first and second spacers and exposing a portion of the hard mask layer and having a longitudinal axis extending in a first direction, forming a block mask covering a middle portion of the first opening, the block mask having a longitudinal axis extending in a second direction different than the first direction, etching the hard mask layer in the presence of the block mask and the first and second spacers to define aligned first and second line segment openings in the hard mask layer extending in the first direction, etching recesses in a dielectric layer disposed beneath the hard mask layer based on the first and second line segment openings, and filling the recesses with a conductive material.
Abstract:
A method of forming an ultra-regular layout with unidirectional M1 metal line and the resulting device are disclosed. Embodiments include forming first and second vertical gate lines, spaced from and parallel to each other; forming a M1 metal line parallel to and between the first and second gate lines; forming first, second, and third M0 metal segments perpendicular to the M1 metal line; connecting the first M0 metal segment to the M1 metal line and the second gate line; connecting the second M0 metal segment to the first gate line and the second gate line; connecting the third M0 metal segment to the first gate line and the M1 metal line; forming a first gate cut on the first gate line between the second and third M0 metal segments; and forming a second gate cut on the second gate line between the first and second M0 segments.
Abstract:
Methods of patterning metallization lines having variable widths in a metallization layer. A first mandrel layer is formed over a mask layer, with the mask layer overlying a second mandrel layer. The first mandrel layer is etched to form mandrel lines that have variable widths. The first non-mandrel trenches are etched in the mask layer, where the non-mandrel trenches have variable widths. The first mandrel lines are used to etch mandrel trenches in the mask layer, so that the mandrel lines and first non-mandrel lines define a mandrel pattern. The second mandrel layer is etched according to the mandrel pattern to form second mandrel lines, with the second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of non-mandrel trenches.
Abstract:
At least one method, apparatus and system disclosed involves providing a functional cell for a circuit layout for an integrated circuit device. A determination as to a first location for a two-dimensional portion of a first power rail in a functional cell is made. A first portion of the first power rail is formed in a first direction. A second portion of the first power rail is formed in a second direction in the first location for the two-dimensional portion.
Abstract:
A dense library architecture using an M0 hand-shake and the method of forming the layout are disclosed. Embodiments include forming first and second active areas on a substrate, at the top and bottom of a cell, separated from each other; forming first through third gate lines perpendicular to the active areas, where the first and third gate lines are dummy gates at the cell edges; forming trench silicide segments on each of the active areas, between the first, second, and third gate lines; forming first and second M1 metal lines between the first and second gate lines and the second and third gate lines, respectively; forming a M0 segment between the first and second active regions perpendicular to the M1 metal lines; forming a CB between the M0 segment and the second gate line; and forming a V0 from the first metal line to the M0 segment.
Abstract:
Disclosed is a semiconductor structure that includes a vertical field effect transistor (VFET) with a U-shaped semiconductor body. The semiconductor structure can be a standard VFET or a feedback VFET. In either case, the VFET includes a lower source/drain region, a semiconductor body on the lower source/drain region, and an upper source/drain region on the top of the semiconductor body. Rather than having an elongated fin shape, the semiconductor body folds back on itself in the Z direction so as to be essentially U-shaped (as viewed from above). Using a U-shaped semiconductor body reduces the dimension of the VFET in the Z direction without reducing the end-to-end length of the semiconductor body. Thus, VFET cell height can be reduced without reducing device drive current or violating critical design rules. Also disclosed is a method of forming a semiconductor structure that includes such a VFET with a U-shaped semiconductor body.