中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

8 records (took 0.014 seconds)

    FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE
    1.
    发明申请
    FORMING SOURCE/DRAIN REGIONS WITH SINGLE RETICLE AND RESULTING DEVICE 审中-公开
    形成来源/排水区域与单一和结果的设备

    公开(公告)号：US20150255353A1

    公开(公告)日：2015-09-10

    申请号：US14197267

    申请日：2014-03-05

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jing WAN ,  Andy WEI ,  Jinping LIU ,  Xiang HU ,  Dae-han CHOI ,  Dae Geun YANG ,  Churamani GAIRE ,  Akshey SEHGAL

    IPC: H01L21/8238 ,  H01L27/092

    CPC classification number: H01L21/823814 ,  H01L21/823821 ,  H01L27/0924

    Abstract: Methods for forming FinFET source/drain regions with a single reticle and the resulting devices are disclosed. Embodiments may include forming a first fin and a second fin above a substrate, forming a gate crossing over the first fin and the second fin, removing portions of the first fin and the second fin on both sides the gate, forming silicon phosphorous tops on the first fin and the second fin in place of the portions, removing the silicon phosphorous tops on the first fin, and forming silicon germanium tops on the first fin in place of the silicon phosphorous tops.

    Abstract translation: 公开了用单个掩模版形成FinFET源极/漏极区域的方法以及所得到的器件。 实施例可以包括在衬底上形成第一鳍片和第二鳍片，形成跨越第一鳍片和第二鳍片的栅极，在栅极的两侧去除第一鳍片和第二鳍片的部分，在第二鳍片上形成硅磷顶部 第一鳍片和第二鳍片代替部分，去除第一鳍片上的磷磷顶部，并且在第一鳍片上形成硅锗顶部代替硅磷顶部。

    PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH
    2.
    发明申请
    PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH 有权
    保持种植层在STI边缘和改善外观生长

    公开(公告)号：US20160343607A1

    公开(公告)日：2016-11-24

    申请号：US14716938

    申请日：2015-05-20

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jing WAN ,  Jer-Hueih(James) CHEN ,  Cuiqin XU ,  Padmaja NAGAIAH

    IPC: H01L21/762 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/28 ,  H01L29/165 ,  H01L21/306 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/308 ,  H01L21/3065

    CPC classification number: H01L29/66795 ,  H01L21/28008 ,  H01L21/3083 ,  H01L21/76232 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7851

    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

    Abstract translation: 形成在Si衬底的部分上延伸的自对准STI区域的方法，以便能够随后在不使用光刻掩模的情况下形成外延生长的嵌入式S / D区域，并且提供所得到的器件。 实施例包括在Si衬底上形成具有横向分开的开口的STI蚀刻掩模; 通过开口将浅沟槽形成Si衬底; 在浅沟槽和开口的相对侧壁上形成第一至第四氧化物间隔物; 在第一和第二氧化物间隔物之间​​以及第三和第四氧化物间隔物之间​​形成深的STI沟槽，进入Si衬底; 在所述第一至第四氧化物间隔物和所述STI蚀刻掩模的一部分上形成STI氧化物层，所述STI氧化物层填充所述深STI沟槽; 并且将STI氧化物层平坦化到STI蚀刻掩模的部分。

    PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH
    3.
    发明申请
    PRESERVING THE SEED LAYER ON STI EDGE AND IMPROVING THE EPITAXIAL GROWTH 审中-公开

    公开(公告)号：US20180286967A1

    公开(公告)日：2018-10-04

    申请号：US15997368

    申请日：2018-06-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jing WAN ,  Jer-Hueih(James) CHEN ,  Cuiqin XU ,  Padmaja NAGAIAH

    IPC: H01L29/66 ,  H01L29/78 ,  H01L29/165 ,  H01L21/28 ,  H01L29/06 ,  H01L21/762 ,  H01L29/08 ,  H01L21/308

    Abstract: A method of forming self-aligned STI regions extending over portions of a Si substrate to enable the subsequent formation of epitaxially grown embedded S/D regions without using a lithography mask and the resulting device are provided. Embodiments include forming a STI etch mask with laterally separated openings over a Si substrate; forming shallow trenches into the Si substrate through the openings; forming first through fourth oxide spacers on opposite sidewalls of the shallow trenches and the openings; forming a deep STI trench between the first and second oxide spacers and between the third and fourth oxide spacers down into the Si substrate; forming a STI oxide layer over the first through fourth oxide spacers and a portion of the STI etch mask, the STI oxide layer filling the deep STI trenches; and planarizing the STI oxide layer down to the portion of the STI etch mask.

    FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS
    7.
    发明申请
    FACILITATING FABRICATING GATE-ALL-AROUND NANOWIRE FIELD-EFFECT TRANSISTORS 有权
    加工制造全门环形纳米效应晶体管

    公开(公告)号：US20150104918A1

    公开(公告)日：2015-04-16

    申请号：US14050494

    申请日：2013-10-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jin Ping LIU ,  Jing WAN ,  Andy WEI

    IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

    CPC classification number: H01L29/66977 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78618 ,  H01L29/78696

    Abstract: Methods are presented for facilitating fabrication of a semiconductor device, such as a gate-all-around nanowire field-effect transistor. The methods include, for instance: providing at least one stack structure including at least one layer or bump extending above the substrate structure; selectively oxidizing at least a portion of the at least one stack structure to form at least one nanowire extending within the stack structure(s) surrounded by oxidized material of the stack structure(s); and removing the oxidized material from the stack structure(s), exposing the nanowire(s). This selectively oxidizing may include oxidizing an upper portion of the substrate structure, such as an upper portion of one or more fins supporting the stack structure(s) to facilitate full 360° exposure of the nanowire(s). In one embodiment, the stack structure includes one or more diamond-shaped bumps or ridges.

    Abstract translation: 提出了用于促进半导体器件的制造的方法，例如栅极全能纳米线场效应晶体管。 所述方法包括例如：提供至少一个堆叠结构，其包括在衬底结构上方延伸的至少一个层或凸块; 选择性地氧化所述至少一个堆叠结构的至少一部分以形成至少一个纳米线，所述至少一个纳米线在由所述堆叠结构的氧化材料包围的所述堆叠结构内延伸; 以及从所述堆叠结构中去除所述氧化的材料，暴露所述纳米线。 这种选择性氧化可以包括氧化衬底结构的上部，例如支撑堆叠结构的一个或多个翅片的上部，以促进纳米线的完全360度曝光。 在一个实施例中，堆叠结构包括一个或多个菱形凸块或凸脊。

    DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION
    8.
    发明申请
    DEVICES AND METHODS OF FORMING FINFETS WITH SELF ALIGNED FIN FORMATION 有权
    具有自对准FIN形成的FINFET形成装置和方法

    公开(公告)号：US20150091094A1

    公开(公告)日：2015-04-02

    申请号：US14043243

    申请日：2013-10-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Jing WAN ,  Andy WEI ,  Lun ZHAO ,  Dae Geun YANG ,  Jin Ping LIU ,  Tien-Ying LUO ,  Guillaume BOUCHE ,  Mariappan HARIHARAPUTHIRAN ,  Churamani GAIRE

    IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84

    CPC classification number: H01L27/0924 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: Devices and methods for forming semiconductor devices with FinFETs are provided. One method includes, for instance: obtaining an intermediate semiconductor device with a substrate and at least one shallow trench isolation region; depositing a hard mask layer over the intermediate semiconductor device; etching the hard mask layer to form at least one fin hard mask; and depositing at least one sacrificial gate structure over the at least one fin hard mask and at least a portion of the substrate. One intermediate semiconductor device includes, for instance: a substrate with at least one shallow trench isolation region; at least one fin hard mask over the substrate; at least one sacrificial gate structure over the at least one fin hard mask; at least one spacer disposed on the at least one sacrificial gate structure; and at least one pFET region and at least one nFET region grown into the substrate.

    Abstract translation: 提供了用FinFET形成半导体器件的器件和方法。 一种方法包括例如：获得具有衬底和至少一个浅沟槽隔离区域的中间半导体器件; 在中间半导体器件上沉积硬掩模层; 蚀刻硬掩模层以形成至少一个翅片硬掩模; 以及在所述至少一个翅片硬掩模和所述基底的至少一部分上沉积至少一个牺牲栅极结构。 一个中间半导体器件包括例如：具有至少一个浅沟槽隔离区域的衬底; 在衬底上的至少一个翅片硬掩模; 至少一个翅片硬掩模上的至少一个牺牲栅极结构; 设置在所述至少一个牺牲栅极结构上的至少一个间隔物; 以及至少一个pFET区域和至少一个生长到衬底中的nFET区域。

Patent Agency Ranking