公开(公告)号：US10312154B2

公开(公告)日：2019-06-04

申请号：US15705888

申请日：2017-09-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/84 ,  H01L21/8234

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a spacer layer that is formed over an endwall of the fin. The spacer layer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US20190252267A1

公开(公告)日：2019-08-15

申请号：US16390232

申请日：2019-04-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Chanro Park ,  Min Gyu Sung ,  Lars Liebmann ,  Su Chen Fan ,  Brent Anderson

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L21/84 ,  H01L29/06 ,  H01L21/8234

CPC classification number: H01L21/823821 ,  H01L21/823431 ,  H01L21/845 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/66583 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/78642

Abstract: A vertical FinFET includes a semiconductor fin formed over a semiconductor substrate. A self-aligned first source/drain contact is electrically separated from a second source/drain contact by a sidewall spacer that is formed over an endwall of the fin. The sidewall spacer, which comprises a dielectric material, allows the self-aligned first source/drain contact to be located in close proximity to an endwall of the fin and the associated second source/drain contact without risk of an electrical short between the adjacent contacts.

公开(公告)号：US10332969B2

公开(公告)日：2019-06-25

申请号：US16167081

申请日：2018-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/788

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

公开(公告)号：US10304833B1

公开(公告)日：2019-05-28

申请号：US15898812

申请日：2018-02-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Bipul C. Paul ,  Ruilong Xie ,  Bartlomiej Jan Pawlak ,  Lars W. Liebmann ,  Daniel Chanemougame ,  Nicholas V. LiCausi ,  Andreas Knorr

IPC: H01L29/775 ,  H01L29/78 ,  H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L27/12

Abstract: A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.

公开(公告)号：US20200035569A1

公开(公告)日：2020-01-30

申请号：US16577032

申请日：2019-09-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/822 ,  H01L27/12 ,  H01L27/092

Abstract: A device is disclosed that includes a first transistor device of a first type and a second transistor device of a second type positioned vertically above the first transistor, wherein the first type and second type of transistors are opposite types. The device also includes a gate structure for the first transistor and the second transistor, wherein the gate structure comprises a first gate electrode for the first transistor and a second gate electrode for the second transistor and a gate stack spacer positioned vertically between the first gate electrode and the second gate electrode so as to electrically isolate the first gate electrode from the second gate electrode.

公开(公告)号：US10446659B2

公开(公告)日：2019-10-15

申请号：US15783270

申请日：2017-10-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Rohit Galatage ,  Puneet Harischandra Suvarna

IPC: H01L29/51 ,  H01L29/49 ,  H01L21/28 ,  H01L23/535 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768

Abstract: A layer of ferroelectric material is incorporated into the gate contact of a metal oxide semiconductor field effect transistor (MOSFET), i.e., outside of the device active area. Flexibility in the deposition and patterning of the ferroelectric layer geometry allows for efficient matching between the capacitance of the ferroelectric layer and the capacitance of the gate, providing a step-up voltage transformer, decreased threshold voltage, and a sub-threshold swing for the device of less than 60 mV/decade.

公开(公告)号：US20190115437A1

公开(公告)日：2019-04-18

申请号：US16167081

申请日：2018-10-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Rohit Galatage ,  Steven Bentley ,  Puneet Harischandra Suvarna ,  Zoran Krivokapic

IPC: H01L29/423 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42324 ,  H01L21/28273 ,  H01L21/28291 ,  H01L29/516 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/6684 ,  H01L29/78391 ,  H01L29/7851 ,  H01L29/788

Abstract: A semiconductor device includes a gate electrode structure that is positioned adjacent to a channel region of a transistor element. The gate electrode structure includes a floating gate electrode portion, a negative capacitor portion, and a ferroelectric material capacitively coupling the floating gate electrode portion to the negative capacitor portion. A first conductive material is positioned between the floating gate electrode portion and the ferroelectric material, wherein a first portion of the first conductive material is embedded in and laterally surrounded by the floating gate electrode portion, and a second conductive material is positioned between the first portion of the first conductive material and the ferroelectric material, wherein the second conductive material is embedded in and laterally surrounded by a second portion of the first conductive material.

公开(公告)号：US20190214469A1

公开(公告)日：2019-07-11

申请号：US15866855

申请日：2018-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bipul C. Paul ,  Ruilong Xie ,  Puneet Harischandra Suvarna

IPC: H01L29/417 ,  H01L29/06 ,  H01L27/092 ,  H01L21/8238 ,  H01L23/48

CPC classification number: H01L29/41733 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/823878 ,  H01L23/481 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0665

Abstract: Structures and circuits including multiple nanosheet field-effect transistors and methods of forming such structures and circuits. A complementary field-effect transistor includes a first nanosheet transistor with a source/drain region and a second nanosheet transistor with a source/drain region stacked over the source/drain region of the first nanosheet transistor. A contact extends vertically to connect the source/drain region of the first nanosheet transistor of the complementary field-effect transistor and the source/drain region of the second nanosheet transistor of the complementary field-effect transistor.

公开(公告)号：US10347745B2

公开(公告)日：2019-07-09

申请号：US15268751

申请日：2016-09-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Puneet Harischandra Suvarna ,  Steven J. Bentley ,  Daniel Chanemougame

IPC: H01L29/66 ,  H01L21/00 ,  H01L29/08 ,  H01L29/165

Abstract: One illustrative method disclosed herein includes, among other things, forming a vertically oriented channel semiconductor structure above a substrate, performing an epi deposition process to simultaneously form at least a portion of a bottom source/drain region and at least a portion of a top source/drain region during the epi deposition process and, after performing the epi deposition process, forming a gate structure around a portion of the vertically oriented channel semiconductor structure.

公开(公告)号：US10236379B2

公开(公告)日：2019-03-19

申请号：US15593651

申请日：2017-05-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven Bentley ,  Puneet Harischandra Suvarna ,  Julien Frougier ,  Bartlomiej Jan Pawlak

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10

Abstract: A fin extends from, and is perpendicular to, a planar surface of a substrate. A self-aligned bottom source/drain conductor is on the substrate adjacent the fin, a bottom insulator spacer is on the bottom source/drain conductor adjacent the fin, and a gate insulator is on a channel portion of the fin. A gate conductor is on the gate insulator, a self-aligned top source/drain conductor contacts the channel portion of the fin distal to the bottom insulator spacer, a top gate length limit insulator is positioned where the channel portion meets the top source/drain conductor, and a bottom gate length limit insulator is positioned where the channel portion meets the bottom insulator spacer. The gate length of the gate conductor is defined by a distance between the gate length limit insulators.