公开(公告)号：US20190312117A1

公开(公告)日：2019-10-10

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US10325824B2

公开(公告)日：2019-06-18

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

公开(公告)号：US10083873B1

公开(公告)日：2018-09-25

申请号：US15613981

申请日：2017-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xing Zhang ,  Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/10

CPC classification number: H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/1033 ,  H01L29/66795 ,  H01L29/785

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor structures with uniform gate heights and methods of manufacture. The structure includes: short channel devices in a first area of an integrated circuit die; and long channel devices in a second area of the integrated circuit die. The long channel devices have a same gate height as the short channel devices.

公开(公告)号：US08987083B1

公开(公告)日：2015-03-24

申请号：US14202985

申请日：2014-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Zhao Lun ,  Xing Zhang

IPC: H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545

Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.

Abstract translation: 在非平面型半导体工艺中，其结构包括N型和P型凸起结构（例如翅片），并且其中不同类型的外延将在N型和P型凸起结构中的每一种上生长，在 选择性地蚀刻在N型和P型凸起结构部分之上的平版印刷阻挡材料以暴露和平坦化栅极盖。 在第一种类型的外延生长之后，对于N和P型外延中的另一种重复该过程。

公开(公告)号：US10700173B2

公开(公告)日：2020-06-30

申请号：US15949730

申请日：2018-04-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi Qi ,  Hsien-Ching Lo ,  Hong Yu ,  Yanping Shen ,  Wei Hong ,  Xing Zhang ,  Ruilong Xie ,  Haiting Wang ,  Hui Zhan ,  Yong Jun Shi

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L21/306 ,  H01L29/66 ,  H01L21/02 ,  H01L21/3105 ,  H01L29/165

Abstract: One illustrative FinFET device disclosed herein includes a source/drain structure that, when viewed in a cross-section taken through the fin in a direction corresponding to the gate width (GW) direction of the device, comprises a perimeter and a bottom surface. The source/drain structure also has an axial length that extends in a direction corresponding to the gate length (GL) direction of the device. The device also includes a metal silicide material positioned on at least a portion of the perimeter of the source/drain structure for at least a portion of the axial length of the source/drain structure and on at least a portion of the bottom surface of the source/drain structure for at least a portion of the axial length of the source/drain structure.

公开(公告)号：US20180358272A1

公开(公告)日：2018-12-13

申请号：US15622061

申请日：2017-06-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mitsuhiro Togo ,  Ram Asra ,  Xing Zhang ,  Palanivel Balasubramaniam

IPC: H01L21/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L22/20 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/82385 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/1037 ,  H01L29/42376

Abstract: At least one method, apparatus and system are disclosed for controlling threshold voltage values for a plurality of transistor devices. Determine a first threshold voltage of a first transistor gate comprising a first gate channel having a first length. Determine a second length of a second gate channel of a second transistor gate. Determining a process adjustment of the second gate based on the second length for providing a second threshold voltage of the second transistor gate. The second threshold voltage is within a predetermined range of the first threshold voltage. Provide data relating to process adjustment to a process controller for performing the process adjustment.

公开(公告)号：US10043713B1

公开(公告)日：2018-08-07

申请号：US15591814

申请日：2017-05-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xinyuan Dou ,  Hong Yu ,  Zhenyu Hu ,  Xing Zhang

IPC: H01L21/84 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/423

Abstract: Methods of reducing the SC GH on a FinFET device while protecting the LC devices and the resulting devices are provided. Embodiments include forming an ILD over a substrate of a FinFET device, the ILD having a SC region and a LC region; forming a SC gate and a LC gate within the SC and LC regions, respectively, an upper surface of the SC and LC gates being substantially coplanar with an upper surface of the ILD; forming a lithography stack over the LC region; recessing the SC gate; stripping the lithography stack; forming a SiN cap layer over the SC and LC regions; forming a TEOS layer over the SiN cap layer; and planarizing the TEOS layer.

公开(公告)号：US09252238B1

公开(公告)日：2016-02-02

申请号：US14461887

申请日：2014-08-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kristina Trevino ,  Yuan-Hung Liu ,  Gabriel Padron Wells ,  Xing Zhang ,  Hoong Shing Wong ,  Chang Ho Maeng ,  Taejoon Han ,  Gowri Kamarthy ,  Isabelle Orain ,  Ganesh Upadhyaya

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3213 ,  H01L29/40

CPC classification number: H01L29/66545 ,  H01L21/28088 ,  H01L21/28194 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/32136 ,  H01L29/4966 ,  H01L29/517

Abstract: Semiconductor structures and fabrication methods are provided which includes, for instance, providing a gate structure over a semiconductor substrate, the gate structure including multiple conformal gate layers and a gate material disposed within the multiple conformal gate layers; recessing a portion of the multiple conformal gate layers below an upper surface of the gate structure, where upper surfaces of recessed, multiple conformal gate layers are coplanar; and removing a portion of the gate material to facilitate an upper surface of a remaining portion of the gate material to be coplanar with an upper surface of the recessed, multiple conformal gate layers.

Abstract translation: 提供半导体结构和制造方法，其包括例如在半导体衬底上提供栅极结构，所述栅极结构包括多个共形栅极层和设置在多个共形栅极层内的栅极材料; 将多个共形栅极层的一部分凹陷在栅极结构的上表面之下，其中凹入的多个共形栅极层的上表面是共面的; 以及去除所述栅极材料的一部分以便于所述栅极材料的剩余部分的上表面与所述凹入的多个共形栅极层的上表面共面。