公开(公告)号：US09059218B2

公开(公告)日：2015-06-16

申请号：US14030506

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC: H01L21/22 ,  H01L29/66 ,  H01L29/78 ,  H01L21/225

CPC classification number: H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract translation: 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。

公开(公告)号：US20150076622A1

公开(公告)日：2015-03-19

申请号：US14030506

申请日：2013-09-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bharat Krishnan ,  Jinping Liu ,  Zhao Lun ,  Hui Zhan ,  Bongki Lee

IPC: H01L29/66 ,  H01L21/225 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/2253 ,  H01L21/2652 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a semiconductor substrate, an active region and a dummy gate structure disposed over the active region. A sacrificial conformal layer, including a bottom oxide layer and a top nitride layer are provided over the dummy gate structure and active region to protect the dummy gate during source and drain implantation. The active region is implanted using dopants such as, a n-type dopant or a p-type dopant to create a source region and a drain region in the active region, after which the sacrificial conformal layer is removed.

Abstract translation: 半导体结构包括设置在有源区上的半导体衬底，有源区和伪栅极结构。 在伪栅极结构和有源区域上设置包括底部氧化物层和顶部氮化物层的牺牲保形层，以在源极和漏极注入期间保护虚拟栅极。 使用诸如n型掺杂剂或p型掺杂剂的掺杂剂注入有源区域，以在有源区域中产生源极区域和漏极区域，之后去除牺牲保形层。

公开(公告)号：US09431528B2

公开(公告)日：2016-08-30

申请号：US14281359

申请日：2014-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Xiang Hu ,  Zhao Lun ,  Huang Liu

IPC: H01L21/311 ,  H01L29/06 ,  H01L29/12 ,  H01L29/78 ,  H01L21/3105 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L29/78 ,  H01L21/02532 ,  H01L21/3081 ,  H01L21/3105 ,  H01L21/31051 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/31144 ,  H01L29/0684 ,  H01L29/12 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A lithographic stack over a raised structure (e.g., fin) of a non-planar semiconductor structure, such as a FinFET, includes a bottom layer of spin-on amorphous carbon or spin-on organic planarizing material, a hard mask layer of a nitride and/or an oxide on the spin-on layer, a layer of a developable bottom anti-reflective coating (dBARC) on the hard mask layer, and a top layer of photoresist. The stack is etched to expose and recess the raised structure, and epitaxial structure(s) are grown on the recess.

Abstract translation: 诸如FinFET的非平面半导体结构的凸起结构（例如，翅片）上的光刻叠层包括旋涂非晶碳或旋涂有机平面化材料的底层，氮化物的硬掩模层 和/或旋涂层上的氧化物，硬掩模层上的可显影底部抗反射涂层（dBARC）的层和光致抗蚀剂的顶层。 蚀刻该叠层以露出和凹进凸起的结构，并且外延结构在凹槽上生长。

公开(公告)号：US09419101B1

公开(公告)日：2016-08-16

申请号：US14932394

申请日：2015-11-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Hong Yu ,  Zhao Lun ,  Tao Han ,  Hsien-Ching Lo ,  Basab Banerjee ,  Wen Zhi Gao ,  Byoung-Gi Min

IPC: H01L21/8232 ,  H01L29/66 ,  H01L29/78 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/6656 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/10879 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming spacers and the resulting fin-shaped field effect transistors are provided. Embodiments include forming a silicon (Si) fin over a substrate; forming a polysilicon gate over the Si fin; and forming a spacer on top and side surfaces of the polysilicon gate, and on exposed upper and side surfaces of the Si fin, the spacer including: a first layer and second layer having a first dielectric constant, and a third layer formed between the first and second layers and having a second dielectric constant, wherein the second dielectric constant is lower than the first dielectric constant.

Abstract translation: 提供了形成间隔物的方法和所得的鳍状场效应晶体管。 实施例包括在衬底上形成硅（Si）鳍; 在Si鳍上形成多晶硅栅极; 以及在所述多晶硅栅极的顶表面和侧表面上形成间隔物，并且在所述Si鳍的暴露的上表面和外表面上，所述间隔物包括：具有第一介电常数的第一层和第二层，以及形成在所述第一 和第二层并具有第二介电常数，其中第二介电常数低于第一介电常数。

公开(公告)号：US20150380515A1

公开(公告)日：2015-12-31

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。

公开(公告)号：US09362176B2

公开(公告)日：2016-06-07

申请号：US14319640

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  HongLiang Shen ,  Zhao Lun ,  Zhenyu Hu ,  Richard J. Carter

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/823481 ,  H01L21/30604 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0653

Abstract: The use of two different materials for shallow trench isolation and deep structural trenches with a dielectric material therein (e.g., flowable oxide and a HARP oxide, respectively) causes non-uniform heights of exposed portions of raised semiconductor structures for non-planar semiconductor devices, due to the different etch rates of the materials. Non-uniform openings adjacent the exposed portions of the raised structures from recessing the isolation and dielectric materials are filled with additional dielectric material to create a uniform top layer of one material (the dielectric material), which can then be uniformly recessed to expose uniform portions of the raised structures.

Abstract translation: 对于浅沟槽隔离和其中具有介电材料的深结构沟槽（例如，可流动的氧化物和HARP氧化物）分别使用两种不同的材料导致用于非平面半导体器件的凸起半导体结构的暴露部分的不均匀高度， 由于材料的蚀刻速率不同。 与凸起结构的暴露部分相邻的不均匀的开口不会使隔离和介电材料凹陷，填充有额外的电介质材料，以形成均匀的一层材料（电介质材料）的顶层，然后可将其均匀地凹入以露出均匀的部分 的凸起结构。

公开(公告)号：US08987083B1

公开(公告)日：2015-03-24

申请号：US14202985

申请日：2014-03-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Zhao Lun ,  Xing Zhang

IPC: H01L21/8238 ,  H01L27/108 ,  H01L29/76 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L29/0657 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66545

Abstract: In a non-planar based semiconductor process where the structure includes both N and P type raised structures (e.g., fins), and where a different type of epitaxy is to be grown on each of the N and P type raised structures, prior to the growing, a lithographic blocking material over one of the N and P type raised structure portions is selectively etched to expose and planarize a gate cap. After the first type of epitaxy is grown, the process is repeated for the other of the N and P type epitaxy.

Abstract translation: 在非平面型半导体工艺中，其结构包括N型和P型凸起结构（例如翅片），并且其中不同类型的外延将在N型和P型凸起结构中的每一种上生长，在 选择性地蚀刻在N型和P型凸起结构部分之上的平版印刷阻挡材料以暴露和平坦化栅极盖。 在第一种类型的外延生长之后，对于N和P型外延中的另一种重复该过程。

公开(公告)号：US09337306B2

公开(公告)日：2016-05-10

申请号：US14319462

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei Peng ,  Xusheng Wu ,  Hong Yu ,  Zhao Lun

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H01L29/6656 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for forming an epitaxial (epi) source/drain (S/D) and/or a semiconductor device having an epi S/D are provided. In embodiments of the invention, a first portion of the epi S/D is formed in the S/D region on a fin in a finned substrate. After the first portion is formed, but before completion of the formation of the S/D, a secondary spacer is formed in the S/D region. Then, the remainder portion of the S/D is formed in the S/D region. As a result, the S/D is separated from the gate stack by the secondary spacer.

Abstract translation: 提供了用于形成外延（epi）源极/漏极（S / D）和/或具有外延S / D的半导体器件的方法。 在本发明的实施例中，epi S / D的第一部分形成在鳍状衬底中的翅片上的S / D区域中。 在形成第一部分之后，但在形成S / D之前，在S / D区域中形成二次间隔物。 然后，在S / D区域中形成S / D的剩余部分。 结果，S / D通过辅助间隔件与栅极堆叠分离。