公开(公告)号：US10672655B2

公开(公告)日：2020-06-02

申请号：US15975611

申请日：2018-05-09

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Basoene Briggs ,  Ivan Zyulkov ,  Katia Devriendt

IPC: H01L21/027 ,  H01L21/768 ,  H01L21/311 ,  H01L21/033 ,  H01L21/288 ,  H01L21/285

Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines. In one aspect, a method for patterning a target layer comprises: forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines, filling the gaps with a sacrificial material, forming a hole by removing the sacrificial material along a portion of one of the gaps, the hole extending across the gap and exposing a surface portion of the target layer and sidewall surface portions of material lines on opposite sides of the one gap, performing a selective deposition process adapted to grow a fill material selectively on the one or more surface portions inside the hole, thereby forming a block mask extending across the gap, removing, selectively to the material lines and the block mask, the sacrificial material from the target layer to expose the gaps, the one gap being interrupted in the longitudinal direction by the block mask, and transferring a pattern including the material lines and the block mask into the target layer.

公开(公告)号：US20170170313A1

公开(公告)日：2017-06-15

申请号：US15351504

申请日：2016-11-15

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Clement Merckling ,  Katia Devriendt ,  Rita Rooyackers

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/16 ,  C30B29/40 ,  H01L21/02 ,  H01L29/66 ,  C30B25/04 ,  H01L29/06 ,  H01L29/20

CPC classification number: H01L29/7827 ,  C30B25/04 ,  C30B29/06 ,  C30B29/08 ,  C30B29/40 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02603 ,  H01L21/02639 ,  H01L21/30621 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31138 ,  H01L29/045 ,  H01L29/0669 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66666 ,  H01L29/66795 ,  H01L29/78642

Abstract: A method of producing a pre-patterned structure comprising at least one cavity for growing a vertical nanostructure is disclosed. The method includes providing at least one protruding structure that extends upwardly from a main surface of a substrate. The at least one protruding structure has a main portion of a first height and an upper portion on the main portion. The method also includes embedding the at least one protruding structure in a dielectric material. Further, the method includes removing at least an excess portion of the dielectric material, thereby exposing a top surface of the upper portion and forming a flattened surface of the top surface of the upper portion and the dielectric material. In addition, the method includes forming at least one cavity of a first depth by removing the upper portion, thereby exposing a top surface of the main portion of the at least one protruding structure.

公开(公告)号：US10395978B2

公开(公告)日：2019-08-27

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/308

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.

公开(公告)号：US20180330986A1

公开(公告)日：2018-11-15

申请号：US15975611

申请日：2018-05-09

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven

Inventor： Basoene Briggs ,  Ivan Zyulkov ,  Katia Devriendt

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/285 ,  H01L21/288 ,  H01L21/033

Abstract: The disclosed technology generally relates to patterning structures in semiconductor fabrication, and more particularly to patterning structures using mask structures having bridged lines. In one aspect, a method for patterning a target layer comprises: forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines, filling the gaps with a sacrificial material, forming a hole by removing the sacrificial material along a portion of one of the gaps, the hole extending across the gap and exposing a surface portion of the target layer and sidewall surface portions of material lines on opposite sides of the one gap, performing a selective deposition process adapted to grow a fill material selectively on the one or more surface portions inside the hole, thereby forming a block mask extending across the gap, removing, selectively to the material lines and the block mask, the sacrificial material from the target layer to expose the gaps, the one gap being interrupted in the longitudinal direction by the block mask, and transferring a pattern including the material lines and the block mask into the target layer.

公开(公告)号：US20180247863A1

公开(公告)日：2018-08-30

申请号：US15907118

申请日：2018-02-27

Applicant: IMEC VZW

Inventor： Basoene Briggs ,  Farid Sebaai ,  Juergen Boemmels ,  Zsolt Tokei ,  Christopher Wilson ,  Katia Devriendt

IPC: H01L21/768 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3213

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.