公开(公告)号：US20170263551A1

公开(公告)日：2017-09-14

申请号：US15529483

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  MANISH CHANDHOK ,  JASMEET S. CHAWLA ,  FLORIAN GSTREIN ,  EUNGNAK HAN ,  RAMI HOURANI ,  KEVIN LIN ,  RICHARD E. SCHENKER ,  TODD R. YOUNKIN

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76849 ,  H01L21/76897 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2221/1026

Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.

公开(公告)号：US20160197011A1

公开(公告)日：2016-07-07

申请号：US14912036

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： ROBERT L. BRISTOL ,  FLORIAN GSTREIN ,  RICHARD E. SCHENKER ,  PAUL A. NYHUS ,  CHARLES H. WALLACE ,  HUI JAE YOO

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L21/76897 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76825 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Subtractive self-aligned via and plug patterning for back end of line (BEOL) interconnects is described. In an example, an interconnect structure for an integrated circuit includes a first layer of the interconnect structure disposed above a substrate. The first layer includes a first grating of alternating metal lines and dielectric lines in a first direction. The dielectric lines have an uppermost surface higher than an uppermost surface of the metal lines. The interconnect structure further includes a second layer of the interconnect structure disposed above the first layer of the interconnect structure. The second layer includes a second grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. The dielectric lines have a lowermost surface lower than a lowermost surface of the metal lines. The dielectric lines of the second grating overlap and contact, but are distinct from, the dielectric lines of the first grating. The metal lines of the first grating are spaced apart from the metal lines of the second grating.

Abstract translation: 描述了用于后端（BEOL）互连的消减自对准通孔和插塞图案。 在一个示例中，用于集成电路的互连结构包括设置在基板上方的互连结构的第一层。 第一层包括在第一方向上交替的金属线和介质线的第一光栅。 介质线具有高于金属线的最上表面的最上表面。 互连结构还包括设置在互连结构的第一层上方的互连结构的第二层。 第二层包括垂直于第一方向的第二方向的交替金属线和介质线的第二光栅。 介质线具有低于金属线的最下表面的最下表面。 第二光栅的介质线与第一光栅的介质线重叠并接触，但不同。 第一光栅的金属线与第二光栅的金属线间隔开。

公开(公告)号：US20180174893A1

公开(公告)日：2018-06-21

申请号：US15898618

申请日：2018-02-18

Applicant: INTEL CORPORATION

Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/31

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：US20170330972A1

公开(公告)日：2017-11-16

申请号：US15527288

申请日：2014-12-19

Applicant: INTEL CORPORATION

Inventor： GRANT KLOSTER ,  SCOTT CLENDENNING ,  Rami HOURANI ,  SZUYA S. LIAO ,  PATRICIO E. ROMERO ,  FLORIAN GSTREIN

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L21/3105 ,  H01L21/311 ,  H01L29/786 ,  H01L23/498

CPC classification number: H01L29/7851 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31133 ,  H01L21/32 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42368 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/786

Abstract: Methods of selectively depositing high-K gate dielectric on a semiconductor structure are disclosed. The method includes providing a semiconductor structure disposed above a semiconductor substrate. The semiconductor structure is disposed beside an isolation sidewall. A sacrificial blocking layer is then selectively deposited on the isolation sidewall and not on the semiconductor structure. Thereafter, a high-K gate dielectric is deposited on the semiconductor structure, but not on the sacrificial blocking layer. Properties of the sacrificial blocking layer prevent deposition of oxide material on its surface. A thermal treatment is then performed to remove the sacrificial blocking layer, thereby forming a high-K gate dielectric only on the semiconductor structure.

公开(公告)号：US20170330794A1

公开(公告)日：2017-11-16

申请号：US15528427

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： RAMI HOURANI ,  MARIE KRYSAK ,  FLORIAN GSTREIN ,  RUTH A. BRAIN ,  MARK T. BOHR

IPC: H01L21/768 ,  H01L23/31 ,  H01L23/528

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.