公开(公告)号：US11574874B2

公开(公告)日：2023-02-07

申请号：US16473598

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Srinivas V. Pietambaram ,  Frank Truong ,  Praneeth Akkinepally ,  Andrew J. Brown ,  Lauren A. Link ,  Prithwish Chatterjee

IPC: H01L23/538 ,  H01L21/48

Abstract: An apparatus system is provided which comprises: a photoimageable dielectric layer; a first interconnect structure formed through the photoimageable dielectric, the first interconnect structure formed at least in part using a lithography process; and a second interconnect structure formed through the photoimageable dielectric, the second interconnect structure formed at least in part using a laser drilling process.

公开(公告)号：US11881463B2

公开(公告)日：2024-01-23

申请号：US17524375

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L25/00 ,  H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

CPC classification number: H01L23/645 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L21/78 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2224/215 ,  H01L2924/0105 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/19042 ,  H01L2924/19103

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US20220285079A1

公开(公告)日：2022-09-08

申请号：US17192187

申请日：2021-03-04

Applicant: Intel Corporation

Inventor： Srinivas Pietambaram ,  Pooya Tadayon ,  Kristof Darmawikarta ,  Tarek Ibrahim ,  Prithwish Chatterjee

IPC: H01F27/28 ,  H01F1/04 ,  H01F27/40 ,  H05K1/16

Abstract: An inductor can be formed in a coreless electronic substrate from magnetic materials and/or fabrication processes that do not result in the magnetic materials leaching into plating and/or etching solutions/chemistries, and results in a unique inductor structure. This may be achieved by forming the inductors from magnetic ferrites. The formation of the electronic substrates may also include process sequences that prevent exposure of the magnetic ferrites to the plating and/or etching solutions/chemistries.

公开(公告)号：US20220230951A1

公开(公告)日：2022-07-21

申请号：US17715380

申请日：2022-04-07

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01L25/16

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US11270959B2

公开(公告)日：2022-03-08

申请号：US15933599

申请日：2018-03-23

Applicant: Intel Corporation

Inventor： Kirstof Darmawikarta ,  Srinivas Pietambaram ,  Prithwish Chatterjee ,  Sri Ranga Sai Boyapati ,  Wei Lun Jen

IPC: H01L23/64 ,  H01F27/28 ,  H01F1/14 ,  H01F1/34 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00 ,  H01F41/04

Abstract: Techniques for fabricating a semiconductor package comprising inductor features and a magnetic film are described. For one technique, fabricating a package includes: forming inductor features comprising a pad and a conductive line on a first build-up layer; forming a raised pad structure on the first build-up layer by fabricating a pillar structure on the pad, wherein a size of the pillar structure is approximately equal or equal to a corresponding size of the pad such that the pillar structure and the pad are aligned or minimally misaligned relative to each other; encapsulating the inductor features and the raised pad structure in a magnetic film; planarizing the magnetic film until top surfaces of the raised pad structure and magnetic film are co-planar; depositing an additional layer on the top surfaces; and forming a via on the raised pad structure by removing portions of the additional layer above the raised pad structure.

公开(公告)号：US20220068847A1

公开(公告)日：2022-03-03

申请号：US17524375

申请日：2021-11-11

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Rahul Jain ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/683 ,  H01L21/78

Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.

公开(公告)号：US20220013265A1

公开(公告)日：2022-01-13

申请号：US17482855

申请日：2021-09-23

Applicant: Intel Corporation

Inventor： Andrew J. Brown ,  Prithwish Chatterjee ,  Lauren A. Link ,  Sai Vadlamani

IPC: H01F1/20 ,  H01L23/498 ,  H01L21/48 ,  H01F41/02 ,  H05K1/18 ,  H01F1/37 ,  H01F1/28

Abstract: An inductor may be fabricated comprising a magnetic material layer and an electrically conductive via or trace extending through the magnetic material layer, wherein the magnetic material layer comprises dielectric magnetic filler particles within a carrier material. Further embodiments may include incorporating the inductor of the present description into an electronic substrate and may further include an integrated circuit device attached to the electronic substrate and the electronic substrate may further be attached to a board, such as a motherboard.

公开(公告)号：US11804455B1

公开(公告)日：2023-10-31

申请号：US17960057

申请日：2022-10-04

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Thomas Sounart ,  Kristof Darmawikarta ,  Henning Braunisch ,  Prithwish Chatterjee ,  Andrew J. Brown

IPC: H01L23/64 ,  H01L23/498 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/642 ,  H01L21/4846 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/16265 ,  H01L2924/19041 ,  H01L2924/19103

Abstract: Embodiments include an electronic package that includes a dielectric layer and a capacitor on the dielectric layer. In an embodiment, the capacitor comprises a first electrode disposed over the dielectric layer and a capacitor dielectric layer over the first electrode. In an embodiment, the capacitor dielectric layer is an amorphous dielectric layer. In an embodiment, the electronic package may also comprise a second electrode over the capacitor dielectric layer.

公开(公告)号：US11335632B2

公开(公告)日：2022-05-17

申请号：US15857238

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： Prithwish Chatterjee ,  Junnan Zhao ,  Sai Vadlamani ,  Ying Wang ,  Rahul Jain ,  Andrew J. Brown ,  Lauren A. Link ,  Cheng Xu ,  Sheng C. Li

IPC: H01L27/28 ,  H01L23/498 ,  H01L21/48 ,  H01F27/28 ,  H01F41/04 ,  H01L25/16 ,  H01L23/00

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.

公开(公告)号：US20220130748A1

公开(公告)日：2022-04-28

申请号：US17567639

申请日：2022-01-03

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L21/48

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.