公开(公告)号：US20180342472A1

公开(公告)日：2018-11-29

申请号：US15771982

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Telesphor KAMGAING ,  Javier A. FALCON ,  Yoshihiro TOMITA ,  Vijay K. NAIR

IPC: H01L23/66 ,  H01L23/00 ,  H01L25/18

Abstract: Embodiments of the invention include a microelectronic device that includes a first die formed with a silicon based substrate and a second die coupled to the first die. The second die is formed with compound semiconductor materials in a different substrate (e.g., compound semiconductor substrate, group III-V substrate). An antenna unit is coupled to the second die. The antenna unit transmits and receives communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20180090471A1

公开(公告)日：2018-03-29

申请号：US15279353

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： Chia-Pin CHIU ,  Yoshihiro TOMITA ,  Yoko SEKIHARA ,  Robert L. SANKMAN

IPC: H01L25/10 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052

Abstract: An apparatus is described that includes a package on package structure. The package on package structure includes an interposer to implement electrical interconnections between an upper package of the package on package structure and a lower package of the package on package structure. The interposer has packed wires, the packed wires have respective polygonal cross sections.

公开(公告)号：US20160343680A1

公开(公告)日：2016-11-24

申请号：US15225757

申请日：2016-08-01

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

公开(公告)号：US20230369071A1

公开(公告)日：2023-11-16

申请号：US18226129

申请日：2023-07-25

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/16 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

CPC classification number: H01L21/563 ,  H01L23/16 ,  H01L23/562 ,  H01L25/0657 ,  H01L24/97 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/81192 ,  H01L2224/92125 ,  H01L2224/48465 ,  H01L2225/06541 ,  H01L2224/13082 ,  H01L2224/73204 ,  H01L2924/1579 ,  H01L2924/3511 ,  H01L2224/81007 ,  H01L2224/14181 ,  H01L2224/0401 ,  H01L2224/97 ,  H01L2224/81191 ,  H01L24/92 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16225 ,  H01L2225/06568 ,  H01L2224/32225 ,  H01L2224/83192 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48228 ,  H01L2225/06513 ,  H01L24/13 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/81203 ,  H01L2224/81211 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2224/81011 ,  H01L24/81 ,  H01L2924/2064 ,  H01L24/83 ,  H01L2224/26175 ,  H01L24/14 ,  H01L24/73 ,  H01L24/16 ,  H01L2924/1434 ,  H01L2225/06517 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/15311

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20220246554A1

公开(公告)日：2022-08-04

申请号：US17721241

申请日：2022-04-14

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Javier A. FALCON ,  Shawna M. LIFF ,  Yoshihiro TOMITA

IPC: H01L23/66 ,  H01L23/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L25/10 ,  H01L25/16

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20180240762A1

公开(公告)日：2018-08-23

申请号：US15773033

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Vijay K. NAIR ,  Javier A. FALCON ,  Shawna M. LIFF ,  Yoshihiro TOMITA

IPC: H01L23/66 ,  H01L25/16 ,  H01L23/498

CPC classification number: H01L23/66 ,  H01L23/48 ,  H01L23/49827 ,  H01L24/00 ,  H01L25/16 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/15192 ,  H01L2924/15321 ,  H01L2924/18161 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104

Abstract: Embodiments of the invention include a microelectronic device that includes a first silicon based substrate having compound semiconductor components. The microelectronic device also includes a second substrate coupled to the first substrate. The second substrate includes an antenna unit for transmitting and receiving communications at a frequency of approximately 4 GHz or higher.

公开(公告)号：US20150194401A1

公开(公告)日：2015-07-09

申请号：US14658089

申请日：2015-03-13

Applicant: INTEL CORPORATION

Inventor： Rajasekaran SWAMINATHAN ,  Leonel R. ARANA ,  Yoshihiro TOMITA ,  Yosuke KANAOKA

IPC: H01L23/00 ,  H01L25/10

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11849 ,  H01L2224/16012 ,  H01L2224/16147 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K3/3452 ,  H05K3/3484 ,  H05K2203/043 ,  H05K2203/083 ,  H05K2203/1476 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.

Abstract translation: 描述形成微电子封装结构的方法。 这些方法可以包括在衬底上形成包含牺牲聚合物的焊膏，将焊膏固化在焊料的回流温度以下，以在导电焊盘上形成固体复合混合凸块，在固体复合混合凸块周围形成模塑料， 并且回流混合凸块，其中牺牲聚合物基本分解。

公开(公告)号：US20200350181A1

公开(公告)日：2020-11-05

申请号：US16915290

申请日：2020-06-29

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18 ,  H01L23/16

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20190341271A1

公开(公告)日：2019-11-07

申请号：US16515981

申请日：2019-07-18

Applicant: Intel Corporation

Inventor： Omkar G. KARHADE ,  Nitin A. DESHPANDE ,  Debendra MALLIK ,  Bassam M. ZIADEH ,  Yoshihiro TOMITA

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/16 ,  H01L25/18

Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.

公开(公告)号：US20180376591A1

公开(公告)日：2018-12-27

申请号：US16118990

申请日：2018-08-31

Applicant: Intel Corporation

Inventor： Yoshihiro TOMITA ,  Joshua D. HEPPNER ,  Shawna M. LIFF ,  Pramod MALATKAR

IPC: H05K1/03 ,  H05K3/00 ,  A41D13/00 ,  A43B1/00 ,  A43B3/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  A41D1/00

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing a magnetic particle embedded flexible substrate, a printed flexible substrate for a magnetic tray, or an electro-magnetic carrier for magnetized or ferromagnetic flexible substrates. For instance, in accordance with one embodiment, there are means disclosed for fabricating a flexible substrate having one or more electrical interconnects to couple with leads of an electrical device; integrating magnetic particles or ferromagnetic particles into the flexible substrate; supporting the flexible substrate with a carrier plate during one or more manufacturing processes for the flexible substrate, in which the flexible substrate is held flat against the carrier plate by an attractive magnetic force between the magnetic particles or ferromagnetic particles integrated with the flexible substrate and a complementary magnetic attraction of the carrier plate; and removing the flexible substrate from the carrier plate subsequent to completion of the one or more manufacturing processes for the flexible substrate. Other related embodiments are disclosed.