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    DYNAMIC PRESENTATION OF INTERCONNECT PROTOCOL CAPABILITY STRUCTURES
    2.
    发明申请
    DYNAMIC PRESENTATION OF INTERCONNECT PROTOCOL CAPABILITY STRUCTURES 审中-公开

    公开(公告)号：US20190340148A1

    公开(公告)日：2019-11-07

    申请号：US16513941

    申请日：2019-07-17

    Applicant: Intel Corporation

    Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

    IPC: G06F13/42 ,  G06F9/445

    Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

    Power control of a memory device through a sideband channel of a memory bus
    3.
    发明授权
    Power control of a memory device through a sideband channel of a memory bus 有权

    公开(公告)号：US10345885B2

    公开(公告)日：2019-07-09

    申请号：US15277936

    申请日：2016-09-27

    Applicant: INTEL CORPORATION

    Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

    IPC: G06F1/324 ,  G06F13/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F1/3225

    Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

    Power Control of a Memory Device Through a Sideband Channel of a Memory Bus
    4.
    发明申请
    Power Control of a Memory Device Through a Sideband Channel of a Memory Bus 审中-公开

    公开(公告)号：US20180088658A1

    公开(公告)日：2018-03-29

    申请号：US15277936

    申请日：2016-09-27

    Applicant: INTEL CORPORATION

    Inventor： Brian R. McFarlane ,  Robert J. Royer ,  Anoop Mukker ,  Eng Hun Ooi ,  Ritesh B. Trivedi

    IPC: G06F1/32

    CPC classification number: G06F1/3275 ,  G06F1/3225 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/00 ,  Y02D10/126 ,  Y02D10/14 ,  Y02D10/172

    Abstract: A method is described that includes choosing between one of two different ways to cause a memory device to enter a specific one of multiple lower power states that each comprise lower power consumption than a highest low power state. The method also includes asserting a first signal on a first signal line that is coupled to a power management controller of the memory device to indicate to the power management controller that a sideband channel of a memory bus that is coupled to the memory device is activated. The method also includes causing the memory device to enter the specific one of the multiple lower power states by also performing the chosen one of a) sending an in-band signal on said memory bus coupled with said asserting of said first signal, said in-band signal specifying the specific one of the multiple lower power states; or, b) sending a second signal on a second signal line that identifies the specific one of the multiple lower power states.

    Dynamic presentation of interconnect protocol capability structures
    5.
    发明授权
    Dynamic presentation of interconnect protocol capability structures 有权

    公开(公告)号：US11704275B2

    公开(公告)日：2023-07-18

    申请号：US17387261

    申请日：2021-07-28

    Applicant: Intel Corporation

    Inventor： Kuan Hua Tan ,  Eng Hun Ooi ,  Ang Li

    IPC: G06F13/42 ,  G06F9/445

    CPC classification number: G06F13/4221 ,  G06F9/44505 ,  G06F2213/0026

    Abstract: A device connected by a link to a host system can include a first port to receive a capability configuration message across a link and a message request receiving logic comprising hardware circuitry to identify a capability of the device identified in the capability configuration message, determine that the capability is to be presented or hidden from operation based on a capability hide enable bit in the capability configuration message, and configure a capability linked list to present or hide the capability based on the determination. The device can also include a message response generator logic comprising hardware circuitry to generate a response message indicating that the capability is to be presented or hidden from operation. The device can include a second port to transmit the response message across the link.

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