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    Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory
    3.
    发明授权
    Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory 有权
    本地缓存行的包含和非包容性跟踪，以避免缓存行内存上的近似存储器读取写入两级系统内存

    公开(公告)号：US09418009B2

    公开(公告)日：2016-08-16

    申请号：US14142045

    申请日：2013-12-27

    Applicant: Intel Corporation

    Inventor： Adrian C. Moga ,  Vedaraman Geetha ,  Bahaa Fahim ,  Robert G. Blankenship ,  Yen-Cheng Liu ,  Jeffrey D. Chamberlain ,  Stephen R. Van Doren

    IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0888

    Abstract: A processor may include a memory controller to interface with a system memory having a near memory and a far memory. The processor may include logic circuitry to cause memory controller to determine whether a write request is generated remotely or locally, and when the write request is generated remotely to instruct the memory controller to perform a read of near memory before performing a write, when the write request is generated locally and a cache line targeted by the write request is in the inclusive state to instruct the memory controller to perform the write without performing a read of near memory, and when the write request is generated locally and the cache line targeted by the write request is in the non-inclusive state to instruct the memory controller to read near memory before performing the write.

    Abstract translation: 处理器可以包括与具有近存储器和远存储器的系统存储器接口的存储器控​​制器。 处理器可以包括逻辑电路，以使存储器控制器确定写入请求是远程生成还是本地生成，并且当写入请求被远程生成以指示存储器控制器在执行写入之前执行近似存储器的读取，当写入 请求在本地生成，并且由写入请求所针对的高速缓存行处于包含状态，以指示存储器控制器执行写入而不执行近似存储器的读取，并且当本地生成写入请求时， 写请求处于非包容状态，以指示存储器控制器在执行写操作之前读取存储器。

    Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline
    5.
    发明授权
    Multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline 有权
    多重队列多资源进入睡眠和唤醒功能，节省了基于重试的管道中的带宽保持

    公开(公告)号：US09207753B2

    公开(公告)日：2015-12-08

    申请号：US14519584

    申请日：2014-10-21

    Applicant: Intel Corporation

    Inventor： James R. Vash ,  Pritpal S. Ahuja ,  Bongjin Jung ,  Jeffrey D. Chamberlain

    IPC: G06F1/32 ,  G06F13/00 ,  G06F13/16 ,  H04L29/00

    CPC classification number: G06F1/3293 ,  G06F13/00 ,  G06F13/1642 ,  H04L29/00 ,  Y02D10/14

    Abstract: Methods and apparatus relating to multiple-queue multiple-resource entry sleep and wakeup for power savings and bandwidth conservation in a retry based pipeline are described. In one embodiment, a bit indicates whether a corresponding queue entry is asleep or awake with respect to arbitration for resources in a retry based pipeline. Furthermore, multiple entries from different queues may be grouped together and multiple resources may be grouped together. Other embodiments are also disclosed.

    Abstract translation: 描述了在基于重试的流水线中与多队列多资源进入睡眠和唤醒功率节省和带宽保持有关的方法和装置。 在一个实施例中，一位指示相应的队列条目是否相对于基于重试的流水线中的资源的仲裁而睡眠或唤醒。 此外，来自不同队列的多个条目可以被分组在一起，并且多个资源可以被分组在一起。 还公开了其他实施例。

    Two level memory full line writes
    9.
    发明授权
    Two level memory full line writes 有权

    公开(公告)号：US10140213B2

    公开(公告)日：2018-11-27

    申请号：US15447767

    申请日：2017-03-02

    Applicant: Intel Corporation

    Inventor： Robert G. Blankenship ,  Jeffrey D. Chamberlain ,  Yen-Cheng Liu ,  Vedaraman Geetha

    IPC: G06F12/08 ,  G06F12/0891 ,  G06F12/0808 ,  G06F12/0831 ,  G06F12/0893 ,  G06F12/126

    Abstract: A memory controller receives a memory invalidation request that references a line of far memory in a two level system memory topology with far memory and near memory, identifies an address of the near memory corresponding to the line, and reads data at the address to determine whether a copy of the line is in the near memory. Data of the address is to be flushed to the far memory if the data includes a copy of another line of the far memory and the copy of the other line is dirty. A completion is sent for the memory invalidation request to indicate that a coherence agent is granted exclusive access to the line. With exclusive access, the line is to be modified to generate a modified version of the line and the address of the near memory is to be overwritten with the modified version of the line.

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