公开(公告)号：US20190355721A1

公开(公告)日：2019-11-21

申请号：US16473891

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  SCOTT J. MADDOX ,  RITESH JHAVERI ,  PRATIK A. PATEL ,  SZUYA S. LIAO ,  ANAND S. MURTHY ,  TAHIR GHANI

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234

Abstract: Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

公开(公告)号：US20190341300A1

公开(公告)日：2019-11-07

申请号：US16473960

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  BENJAMIN CHU-KUNG ,  SEUNG HOON SUNG ,  JACK T. KAVALIEROS ,  TAHIR GHANI

IPC: H01L21/768 ,  H01L29/49 ,  H01L29/423 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/06

Abstract: Techniques are disclosed for forming transistors employing a carbon-based etch stop layer (ESL) for preserving source and drain (S/D) material during contact trench etch processing. As can be understood based on this disclosure, carbon-based layers can provide increased resistance for etch processing, such that employing a carbon-based ESL on S/D material can preserve that S/D material during contact trench etch processing. This is due to carbon-based layers being able to provide more robust (e.g., more selective) etch selectivity during contact trench etch processing than the S/D material it is preserving (e.g., Si, SiGe, Ge, group III-V semiconductor material) and other etch stop layers (e.g., insulator material-based etch stop layers). Employing a carbon-based ESL enables a given S/D region to protrude from shallow trench isolation (STI) material prior to contact metal deposition, thereby providing more surface area for making contact to the given S/D region, which improves transistor performance.

公开(公告)号：US20180108750A1

公开(公告)日：2018-04-19

申请号：US15573168

申请日：2015-06-12

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  HEI KAM ,  TAHIR GHANI ,  KARTHIK JAMBUNATHAN ,  CHANDRA S. MOHAPATRA

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/8256 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/6681 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8256 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/7848

Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.

公开(公告)号：US20190207015A1

公开(公告)日：2019-07-04

申请号：US16322815

申请日：2016-09-27

Applicant: INTEL CORPORATION

Inventor： RISHABH MEHANDRU ,  CORY E. WEBER ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  JIONG ZHANG ,  RITESH JHAVERI ,  SZUYA S. LIAO

IPC: H01L29/66 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/32 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Techniques are disclosed for forming increasing channel region tensile strain in n-MOS devices. In some cases, increased channel region tensile strain can be achieved via S/D material engineering that deliberately introduces dislocations in one or both of the S/D regions to produce tensile strain in the adjacent channel region. In some such cases, the S/D material engineering to create desired dislocations may include using a lattice mismatched epitaxial S/D film adjacent to the channel region. Numerous material schemes for achieving multiple dislocations in one or both S/D regions will be apparent in light of this disclosure. In some cases, a cap layer can be formed on an S/D region to reduce contact resistance, such that the cap layer is an intervening layer between the S/D region and S/D contact. The cap layer includes different material than the underlying S/D region and/or a higher dopant concentration to reduce contact resistance.

公开(公告)号：US20180158841A1

公开(公告)日：2018-06-07

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  ANAND S. MURTHY ,  DANIEL B. AUBERTINE ,  TAHIR GHANI ,  JACK T. KAVALIEROS ,  BENJAMIN CHU-KUNG ,  CHANDRA S. MOHAPATRA ,  KARTHIK JAMBUNATHAN ,  GILBERT DEWEY ,  WILLY RACHMADY

IPC: H01L27/12 ,  H01L29/161 ,  H01L29/20 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L27/1211 ,  H01L21/76224 ,  H01L21/845 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/20 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

公开(公告)号：US20180151677A1

公开(公告)日：2018-05-31

申请号：US15576150

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  YING PANG ,  ANAND S. MURTHY ,  TAHIR GHANI ,  KARTHIK JAMBUNATHAN

IPC: H01L29/40 ,  H01L27/092 ,  H01L29/78 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8238 ,  H01L29/66

Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.

公开(公告)号：US20180358440A1

公开(公告)日：2018-12-13

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： CHANDRA S. MOHAPATRA ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  KARTHIK JAMBUNATHAN ,  WILLY RACHMADY ,  GILBERT DEWEY ,  TAHIR GHANI ,  JACK T. KAVALIEROS

IPC: H01L29/10 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L29/1054 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/42392 ,  H01L29/66356 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7391 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

公开(公告)号：US20180247939A1

公开(公告)日：2018-08-30

申请号：US15754871

申请日：2015-09-25

Applicant: INTEL CORPORATION

Inventor： GLENN A. GLASS ,  PRASHANT MAJHI ,  ANAND S. MURTHY ,  TAHIR GHANI ,  DANIEL B. AUBERTINE ,  HEIDI M. MEYER ,  KARTHIK JAMBUNATHAN ,  GOPINATH BHIMARASETTI

IPC: H01L27/092 ,  H01L29/10 ,  H01L29/08 ,  H01L29/36 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02

CPC classification number: H01L27/0924 ,  B82Y10/00 ,  H01L21/02238 ,  H01L21/2252 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/324 ,  H01L21/76205 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1079 ,  H01L29/36 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78696

Abstract: Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.

公开(公告)号：US20170330966A1

公开(公告)日：2017-11-16

申请号：US15525183

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  CHANDRA S. MOHAPATRA ,  ANAND S. MURTHY ,  STEPHEN M. CEA ,  TAHIR GHANI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/7831 ,  H01L29/0607 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785

Abstract: An embodiment includes an apparatus comprising: a fin structure on a substrate, the fin structure including fin top and bottom portions, a channel including a majority carrier, and an epitaxial (EPI) layer; an insulation layer including insulation layer top and bottom portions adjacent the fin top and bottom portions; wherein (a) the EPI layer comprises one or more of group IV and III-V materials, (b) the fin bottom portion includes a fin bottom portion concentration of dopants of opposite polarity to the majority carrier, (c) the fin top portion includes a fin top portion concentration of the dopants less than the fin bottom portion concentration, (d) the insulation layer bottom portion includes an insulation layer bottom portion concentration of the dopants, and (e) the insulation layer top portion includes an insulation top layer portion concentration greater than the insulation bottom portion concentration. Other embodiments are described herein.

公开(公告)号：US20190189785A1

公开(公告)日：2019-06-20

申请号：US16326845

申请日：2016-09-28

Applicant: INTEL CORPORATION

Inventor： KARTHIK JAMBUNATHAN ,  GLENN A. GLASS ,  ANAND S. MURTHY ,  JACK T. KAVALIEROS ,  SEUNG HOON SUNG ,  BENJAMIN CHU-KUNG ,  TAHIR GHANI

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66803 ,  H01L29/10 ,  H01L29/1025 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/7851

Abstract: Integrated circuit transistor structures are disclosed that include a gate structure that is lattice matched to the underlying channel. In particular, the gate dielectric is lattice matched to the underlying semiconductor channel material, and in some embodiments, so is the gate electrode. In an example embodiment, single crystal semiconductor channel material and single crystal gate dielectric material that are sufficiently lattice matched to each other are epitaxially deposited. In some cases, the gate electrode material may also be a single crystal material that is lattice matched to the semiconductor channel material, thereby allowing the gate electrode to impart strain on the channel via the also lattice matched gate dielectric. A gate dielectric material that is lattice matched to the channel material can be used to reduce interface trap density (Dit). The techniques can be used in both planar and non-planar (e.g., finFET and nanowire) metal oxide semiconductor (MOS) transistor architectures.