公开(公告)号：US10249490B2

公开(公告)日：2019-04-02

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. Chau ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Matthew V. Metz ,  Niloy Mukherjee ,  Nancy M. Zelick ,  Gilbert Dewey ,  Willy Rachmady ,  Marko Radosavljevic ,  Van H. Le ,  Ravi Pillarisetty ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8252 ,  H01L27/092 ,  H01L29/06 ,  H01L29/165 ,  H01L29/205 ,  H01L29/10 ,  H01L29/16 ,  H01L29/20

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20170194142A1

公开(公告)日：2017-07-06

申请号：US15464888

申请日：2017-03-21

Applicant: Intel Corporation

Inventor： Niti Goel ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66

CPC classification number: H01L29/205 ,  H01L21/02381 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L29/0607 ,  H01L29/20 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/785

Abstract: A first III-V material based buffer layer is deposited on a silicon substrate. A second III-V material based buffer layer is deposited onto the first III-V material based buffer layer. A III-V material based device channel layer is deposited on the second III-V material based buffer layer.

公开(公告)号：US09698013B2

公开(公告)日：2017-07-04

申请号：US14908987

申请日：2013-09-04

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Niti Goel ,  Sanaz K. Gardner ,  Pragyansri Pathi ,  Matthew V. Metz ,  Sansaptak Dasgupta ,  Seung Hoon Sung ,  James M. Powers ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Jack T. Kavalieros ,  Robert S. Chau

IPC: H01L21/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L21/762

CPC classification number: H01L21/02694 ,  H01L21/02381 ,  H01L21/02516 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/76224 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8258 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/267 ,  H01L29/7848

Abstract: Trenches (and processes for forming the trenches) are provided that reduce or prevent crystaline defects in selective epitaxial growth of type III-V or Germanium (Ge) material (e.g., a “buffer” material) from a top surface of a substrate material. The defects may result from collision of selective epitaxial sidewall growth with oxide trench sidewalls. Such trenches include (1) a trench having sloped sidewalls at an angle of between 40 degrees and 70 degrees (e.g., such as 55 degrees) with respect to a substrate surface; and/or (2) a combined trench having an upper trench over and surrounding the opening of a lower trench (e.g., the lower trench may have the sloped sidewalls, short vertical walls, or tall vertical walls). These trenches reduce or prevent defects in the epitaxial sidewall growth where the growth touches or grows against vertical sidewalls of a trench it is grown in.

公开(公告)号：US20170154981A1

公开(公告)日：2017-06-01

申请号：US15430348

申请日：2017-02-10

Applicant: Intel Corporation

Inventor： Niti Goel ,  Benjamin Chu-Kung ,  Sansaptak Dasgupta ,  Niloy Mukherjee ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Robert S. Chau ,  Ravi Pillarisetty

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L21/823807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02647 ,  H01L21/76224 ,  H01L21/76248 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/845 ,  H01L29/66795

Abstract: Electronic device fins may be formed by epitaxially growing a first layer of material on a substrate surface at a bottom of a trench formed between sidewalls of shallow trench isolation (STI) regions. The trench height may be at least 1.5 times its width, and the first layer may fill less than the trench height. Then a second layer of material may be epitaxially grown on the first layer in the trench and over top surfaces of the STI regions. The second layer may have a second width extending over the trench and over portions of top surfaces of the STI regions. The second layer may then be patterned and etched to form a pair of electronic device fins over portions of the top surfaces of the STI regions, proximate to the trench. This process may avoid crystaline defects in the fins due to lattice mismatch in the layer interfaces.

公开(公告)号：US08872225B2

公开(公告)日：2014-10-28

申请号：US13722824

申请日：2012-12-20

Applicant: Intel Corporation

Inventor： Benjamin Chu-Kung ,  Van Le ,  Robert Chau ,  Sansaptak Dasgupta ,  Gilbert Dewey ,  Niti Goel ,  Jack Kavalieros ,  Matthew Metz ,  Niloy Mukherjee ,  Ravi Pillarisetty ,  Willy Rachmady ,  Marko Radosavljevic ,  Han Wui Then ,  Nancy Zelick

IPC: H01L21/02 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/785

Abstract: An embodiment uses a very thin layer nanostructure (e.g., a Si or SiGe fin) as a template to grow a crystalline, non-lattice matched, epitaxial (EPI) layer. In one embodiment the volume ratio between the nanostructure and EPI layer is such that the EPI layer is thicker than the nanostructure. In some embodiments a very thin bridge layer is included between the nanostructure and EPI. An embodiment includes a CMOS device where EPI layers covering fins (or that once covered fins) are oppositely polarized from one another. An embodiment includes a CMOS device where an EPI layer covering a fin (or that once covered a fin) is oppositely polarized from a bridge layer covering a fin (or that once covered a fin). Thus, various embodiments are disclosed from transferring defects from an EPI layer to a nanostructure (that is left present or removed). Other embodiments are described herein.

Abstract translation: 一个实施例使用非常薄的层纳米结构（例如，Si或SiGe鳍）作为模板来生长晶体，非晶格匹配的外延（EPI）层。 在一个实施方案中，纳米结构和EPI层之间的体积比使得EPI层比纳米结构厚。 在一些实施例中，在纳米结构和EPI之间包括非常薄的桥接层。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层彼此相反地极化。 一个实施例包括一个CMOS器件，其中覆盖翅片（或一旦被覆盖的翅片）的EPI层与覆盖翅片（或一旦被覆盖的翅片）的桥接层相反地偏振。 因此，从EPI层转移到纳米结构（剩下的存在或去除）的缺陷中公开了各种实施例。 本文描述了其它实施例。

公开(公告)号：US10268122B2

公开(公告)日：2019-04-23

申请号：US15124810

申请日：2014-07-08

Applicant: INTEL CORPORATION

Inventor： Silvio E. Bou-Ghazale ,  Abhik Ghosh ,  Niti Goel

IPC: G03F7/20 ,  G11C5/02 ,  G11C29/00 ,  G06F17/50 ,  G06F11/20

Abstract: Techniques are disclosed for achieving size reduction of embedded memory arrays through determining a spare-core layout. In an embodiment, input parameters comprising global process parameters are combined with design characteristics to compute yield values corresponding to potential redundancy configurations for a die. Resulting yields may be compared to determine which redundancy configuration is suitable to maintain a particular yield. A die configured with one or more spare cores (with no redundant memory therein) results in a yield which is equivalent to, or exceeds, the yield of a die with conventional memory redundancies. In some example cases, memory redundancy is eliminated from cores. Another embodiment provides a semiconductor structure having including an array of redundant cores, each including a composition of memory arrays and logic structures, wherein at least one of the memory arrays of each redundant core is implemented without at least one of row redundancy and column redundancy.

公开(公告)号：US09923087B2

公开(公告)日：2018-03-20

申请号：US15410681

申请日：2017-01-19

Applicant: Intel Corporation

Inventor： Sansaptak Dasgupta ,  Han Wui Then ,  Marko Radosavljevic ,  Niloy Mukherjee ,  Niti Goel ,  Sanaz Kabehie Gardner ,  Seung Hoon Sung ,  Ravi Pillarisetty ,  Robert S. Chau

IPC: H01L29/66 ,  H01L29/778 ,  H01L29/205 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/223 ,  H01L29/08 ,  H01L29/20 ,  H01L29/207 ,  H01L29/423

CPC classification number: H01L29/7784 ,  H01L21/0254 ,  H01L21/2233 ,  H01L21/2236 ,  H01L21/2654 ,  H01L21/26546 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/0847 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/207 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: Embodiments include high electron mobility transistors (HEMT). In embodiments, a gate electrode is spaced apart by different distances from a source and drain semiconductor region to provide high breakdown voltage and low on-state resistance. In embodiments, self-alignment techniques are applied to form a dielectric liner in trenches and over an intervening mandrel to independently define a gate length, gate-source length, and gate-drain length with a single masking operation. In embodiments, III-N HEMTs include fluorine doped semiconductor barrier layers for threshold voltage tuning and/or enhancement mode operation.

公开(公告)号：US09570614B2

公开(公告)日：2017-02-14

申请号：US14914102

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Sansaptak Dasgupta ,  Niti Goel ,  Van H. Le ,  Marko Radosavljevic ,  Gilbert Dewey ,  Niloy Mukherjee ,  Matthew V. Metz ,  Willy Rachmady ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Harold W. Kennel ,  Stephen M. Cea ,  Robert S. Chau

IPC: H01L29/78 ,  H01L29/165 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/267

CPC classification number: H01L29/785 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/267 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

Abstract: Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation and methods of fabricating such Ge and III-V channel semiconductor devices are described. For example, a semiconductor device includes a semiconductor fin disposed above a semiconductor substrate. The semiconductor fin has a central protruding or recessed segment spaced apart from a pair of protruding outer segments along a length of the semiconductor fin. A cladding layer region is disposed on the central protruding or recessed segment of the semiconductor fin. A gate stack is disposed on the cladding layer region. Source/drain regions are disposed in the pair of protruding outer segments of the semiconductor fin.

Abstract translation: 描述了具有最大化顺应性和自由表面弛豫的Ge和III-V沟道半导体器件以及制造这种Ge和III-V沟道半导体器件的方法。 例如，半导体器件包括设置在半导体衬底之上的半导体鳍。 半导体鳍片具有沿着半导体鳍片的长度与一对突出外部部分间隔开的中心突出或凹陷部分。 在半导体翅片的中央突出或凹陷部分上设置包覆层区域。 栅极堆叠设置在包覆层区域上。 源极/漏极区域设置在半导体鳍片的一对突出的外部段中。

公开(公告)号：US20140231871A1

公开(公告)日：2014-08-21

申请号：US14263708

申请日：2014-04-28

Applicant: INTEL CORPORATION

Inventor： Niti Goel ,  Ravi Pillarisetty ,  Niloy Mukherjee ,  Robert S. Chau ,  Willy Rachmady ,  Matthew V. Metz ,  Van H. Le ,  Jack T. Kavalieros ,  Marko Radosavljevic ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Seung Hoon Sung

IPC: H01L29/78 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/0245 ,  H01L21/02538 ,  H01L21/823807 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7849 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/78696

Abstract: An apparatus including a device including a channel material having a first lattice structure on a well of a well material having a matched lattice structure in a buffer material having a second lattice structure that is different than the first lattice structure. A method including forming a trench in a buffer material; forming an n-type well material in the trench, the n-type well material having a lattice structure that is different than a lattice structure of the buffer material; and forming an n-type transistor. A system including a computer including a processor including complimentary metal oxide semiconductor circuitry including an n-type transistor including a channel material, the channel material having a first lattice structure on a well disposed in a buffer material having a second lattice structure that is different than the first lattice structure, the n-type transistor coupled to a p-type transistor.

Abstract translation: 一种装置，包括在具有与第一格子结构不同的第二格子结构的缓冲材料中具有匹配的晶格结构的阱材料的阱上具有第一晶格结构的沟道材料的装置。 一种包括在缓冲材料中形成沟槽的方法; 在沟槽中形成n型阱材料，n型阱材料具有与缓冲材料的晶格结构不同的晶格结构; 并形成n型晶体管。 一种包括计算机的系统，包括处理器，所述处理器包括互补的金属氧化物半导体电路，所述辅助金属氧化物半导体电路包括包括沟道材料的n型晶体管，所述沟道材料在布置在具有不同于 第一晶格结构，n型晶体管耦合到p型晶体管。

公开(公告)号：US10693008B2

公开(公告)日：2020-06-23

申请号：US14914906

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Niloy Mukherjee ,  Marko Radosavljevic ,  Jack T. Kavalieros ,  Ravi Pillarisetty ,  Niti Goel ,  Van H. Le ,  Gilbert Dewey ,  Benjamin Chu-Kung

IPC: H01L31/0256 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/786

Abstract: An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.