公开(公告)号：US20230260914A1

公开(公告)日：2023-08-17

申请号：US18139275

申请日：2023-04-25

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5381 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/1703 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20230207522A1

公开(公告)日：2023-06-29

申请号：US17561720

申请日：2021-12-24

Applicant: Intel Corporation

Inventor： Omkar KARHADE ,  Nitin A. DESHPANDE ,  Ravindranath V. MAHAJAN

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/538 ,  H01L23/48 ,  H01L23/498 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L21/568 ,  H01L21/561 ,  H01L23/5389 ,  H01L23/481 ,  H01L23/49816 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105

Abstract: Embodiments disclosed herein include die modules and methods of making die modules. In an embodiment, a die module comprises a first die with a set of first pads with surfaces that are substantially coplanar with a surface of a first dielectric layer. In an embodiment, the die module further comprises a second die with a set of second pads with surfaces that are substantially coplanar with a surface of a second dielectric layer. In an embodiment the first pads are bonded to the second pads and the first dielectric layer is bonded to the second dielectric layer.

公开(公告)号：US20220238402A1

公开(公告)日：2022-07-28

申请号：US17720202

申请日：2022-04-13

Applicant: Intel Corporation

Inventor： Mitul MODI ,  Robert L. SANKMAN ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Amruthavalli P. ALUR ,  Yikang DENG ,  Eric J. LI

IPC: H01L23/13 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: An apparatus is provided which comprises: a plurality of dielectric layers forming a substrate, a plurality of first conductive contacts on a first surface of the substrate, a cavity in the first surface of the substrate defining a second surface parallel to the first surface, a plurality of second conductive contacts on the second surface of the substrate, one or more integrated circuit die(s) coupled with the second conductive contacts, and mold material at least partially covering the one or more integrated circuit die(s) and the first conductive contacts. Other embodiments are also disclosed and claimed.

公开(公告)号：US20210035911A1

公开(公告)日：2021-02-04

申请号：US16524748

申请日：2019-07-29

Applicant: Intel Corporation

Inventor： Sanka GANESAN ,  Kevin MCCARTHY ,  Leigh M. TRIBOLET ,  Debendra MALLIK ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L23/367 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

Abstract: Embodiments include semiconductor packages and methods to form the semiconductor packages. A semiconductor package includes a bridge over a glass patch. The bridge is coupled to the glass patch with an adhesive layer. The semiconductor package also includes a high-density packaging (HDP) substrate over the bridge and the glass patch. The HDP substrate is conductively coupled to the glass patch with a plurality of through mold vias (TMVs). The semiconductor package further includes a plurality of dies over the HDP substrate, and a first encapsulation layer over the TMVs, the bridge, the adhesive layer, and the glass patch. The HDP substrate includes a plurality of conductive interconnects that conductively couple the dies to the bridge and glass patch. The bridge may be an embedded multi-die interconnect bridge (EMIB), where the EMIB is communicatively coupled to the dies, and the glass patch includes a plurality of through glass vias (TGVs).

公开(公告)号：US20200211969A1

公开(公告)日：2020-07-02

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： MD Altaf HOSSAIN ,  Ankireddy NALAMALPU ,  Dheeraj SUBBAREDDY ,  Robert SANKMAN ,  Ravindranath V. MAHAJAN ,  Debendra MALLIK ,  Ram S. VISWANATH ,  Sandeep B. SANE ,  Sriram SRINIVASAN ,  Rajat AGARWAL ,  Aravind DASU ,  Scott WEBER ,  Ravi GUTALA

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20230307379A1

公开(公告)日：2023-09-28

申请号：US17703768

申请日：2022-03-24

Applicant: Intel Corporation

Inventor： Phil GENG ,  Patrick NARDI ,  Ravindranath V. MAHAJAN ,  Dingying David XU ,  Prasanna RAGHAVAN ,  John HARPER ,  Sanjoy SAHA ,  Yang JIAO

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/49816

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate, and a die coupled to the package substrate. In an embodiment, the electronic package further comprises a stiffener on the package substrate surrounding the die. In an embodiment, the stiffener is a ring with one or more corner regions and one or more beams. In an embodiment, each beam is between a pair of corner regions, and the one or more corner regions have a first thickness and the one or more beams have a second thickness that is greater than the first thickness.

公开(公告)号：US20220196943A1

公开(公告)日：2022-06-23

申请号：US17131621

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Xiaoqian LI ,  Nitin DESHPANDE ,  Omkar KARHADE ,  Ravindranath V. MAHAJAN

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/367

Abstract: A semiconductor package comprises an interposer and a photonics die. The photonics die has a front side with an on-chip fiber connector and solder bumps, the photonics die over the interposer with the on-chip fiber connector and the solder bumps facing away from the interposer. A patch substrate is mounted on the interposer adjacent to the photonics die. A logic die is mounted on the patch substrate with an overhang past an edge of the patch substrate and the overhang is attached to the solder bumps of the photonics die. An integrated heat spreader (IHS) is over the logic die such that the photonics die does not directly contact the IHS.

公开(公告)号：US20220139896A1

公开(公告)日：2022-05-05

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Mark T. BOHR ,  Rajesh KUMAR ,  Robert L. SANKMAN ,  Ravindranath V. MAHAJAN ,  Wesley D. MC CULLOUGH

IPC: H01L25/18 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/16 ,  H01L23/522 ,  H01L23/48 ,  H01L23/538 ,  H01L23/498

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US20200258759A1

公开(公告)日：2020-08-13

申请号：US16635539

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Wilfred GOMES ,  Ravindranath V. MAHAJAN ,  Ram S. VISWANATH

IPC: H01L21/48 ,  H01L23/31 ,  H01L21/56 ,  H01L23/367

Abstract: Techniques and mechanisms for conducting heat with a packaged integrated circuit (IC) device. In an embodiment, the IC device comprises a package substrate and one or more IC dies coupled thereto, where a thermal conductor of the IC device extends through the package substrate. A thermal conductivity of the thermal conductor is more than 20 Watts per meter per degree Kelvin (W/mK). In another embodiment, thermal conductor further extends at least partially through a mold compound disposed on the one or more IC dies.

公开(公告)号：US20170268972A1

公开(公告)日：2017-09-21

申请号：US15075090

申请日：2016-03-18

Applicant: Intel Corporation

Inventor： Vijay Krishnan SUBRAMANIAN ,  Steven A. KLEIN ,  Rajendra C. DIAS ,  Pramod MALATKAR ,  Aleksandar ALEKSOV ,  Ravindranath V. MAHAJAN ,  Robert L. SANKMAN

IPC: G01N3/08

CPC classification number: G01N3/08 ,  G01N2203/0085

Abstract: Embodiments are generally directed to a lateral expansion apparatus for mechanical testing of stretchable electronics. An embodiment of a system includes a compressible cylinder to apply mechanical forces to a stretchable electronics device by the compression and release of the compressible cylinder; a compression unit to compress to the compressible cylinder, wherein the compression unit is to apply a compression force in a direction along an axis of the compressible cylinder to generate lateral expansion of the compressible cylinder; and a testing logic to control compression and release of the compressible cylinder.