公开(公告)号：US20200098698A1

公开(公告)日：2020-03-26

申请号：US16143212

申请日：2018-09-26

Applicant: Intel Corporation

Inventor： Richard PATTEN ,  David O'SULLIVAN ,  Georg SEIDEMANN ,  Bernd WAIDHAS

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/522

Abstract: Embodiments include semiconductor packages, such as wafer level chip scale packages (WLCSPs), flip chip chip scale packages (FCCSPs), and fan out packages. The WLCSP includes a first doped region on a second doped region, a dielectric on a redistribution layer, where the dielectric is between the redistribution layer and doped regions. The WLCSP also includes a shield over the doped regions, the dielectric, and the redistribution layer, where the shield includes a plurality of surfaces, and at least one of the plurality of surfaces of the shield is on a top surface of the first doped region. The WLCSP may have interconnects coupled to the second doped region and redistribution layer. The shield may be a conductive shield that is coupled to ground, and the shield may be directly coupled to the redistribution layer and first doped region. The first and second doped regions may include highly doped n-type materials.

公开(公告)号：US20230343766A1

公开(公告)日：2023-10-26

申请号：US18217000

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： David O'SULLIVAN ,  Georg SEIDEMANN ,  Richard PATTEN ,  Bernd WAIDHAS

IPC: H01L25/10 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L25/105 ,  H01L23/5384 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/565 ,  H01L24/19 ,  H01L24/96 ,  H01L25/50 ,  H01L23/3114 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20240213225A1

公开(公告)日：2024-06-27

申请号：US18601774

申请日：2024-03-11

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/486 ,  H01L23/3107 ,  H01L23/48 ,  H01L23/49827 ,  H01L23/5384 ,  H01L24/19 ,  H01L24/20 ,  H01L24/25 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0652 ,  H01L25/50 ,  H01L21/561 ,  H01L21/568 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5389 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/2518 ,  H01L2224/73259 ,  H01L2224/81005 ,  H01L2224/92224 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/3511

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.

公开(公告)号：US20190019777A1

公开(公告)日：2019-01-17

申请号：US15749760

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Yong SHE ,  John G. MEYERS ,  Zhicheng DING ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/49 ,  H01L23/00 ,  H01L23/50 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/488 ,  H01L23/49 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/09 ,  H01L24/19 ,  H01L24/20 ,  H01L24/32 ,  H01L24/33 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/96 ,  H01L25/50 ,  H01L2224/0231 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48249 ,  H01L2224/73215 ,  H01L2224/73217 ,  H01L2224/73267 ,  H01L2224/83007 ,  H01L2224/92174 ,  H01L2224/92244 ,  H01L2225/0651 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2224/29099 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: Techniques and mechanisms for interconnecting stacked integrated circuit (IC) dies. In an embodiment, a first end of a wire is coupled to a first IC die of a stack, where a second end of the wire is further anchored to the stack independent of the coupled first end. A package material is subsequently disposed around IC dies of the stack and a first portion of the wire that includes the first end. Two-point anchoring of the wire to the stack aids in providing mechanical support to resist movement that might otherwise displace and/or deform the wire while the package material is deposited. In another embodiment, the first portion of the wire is separated from the rest of the wire, and a redistribution Layer is coupled to the first portion to enable interconnection between the first IC die and another IC die of the stack.

公开(公告)号：US20250167183A1

公开(公告)日：2025-05-22

申请号：US19034153

申请日：2025-01-22

Applicant: Intel Corporation

Inventor： David O'SULLIVAN ,  Georg SEIDEMANN ,  Richard PATTEN ,  Bernd WAIDHAS

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

Abstract: Embodiments include semiconductor packages and a method of forming the semiconductor packages. A semiconductor package includes a mold over and around a first die and a first via. The semiconductor package has a conductive pad of a first redistribution layer disposed on a top surface of the first die and/or a top surface of the mold. The semiconductor package includes a second die having a solder ball coupled to a die pad on a bottom surface of the second die, where the solder ball of the second die is coupled to the first redistribution layer. The first redistribution layer couples the second die to the first die, where the second die has a first edge and a second edge, and where the first edge is positioned within a footprint of the first die and the second edge is positioned outside the footprint of the first die.

公开(公告)号：US20220108976A1

公开(公告)日：2022-04-07

申请号：US17553679

申请日：2021-12-16

Applicant: Intel Corporation

Inventor： Georg SEIDEMANN ,  Klaus REINGRUBER ,  Christian GEISSLER ,  Sven ALBERS ,  Andreas WOLTER ,  Marc DITTES ,  Richard PATTEN

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31 ,  H01L23/538

Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.