公开(公告)号：US20230171114A1

公开(公告)日：2023-06-01

申请号：US17537605

申请日：2021-11-30

Applicant: International Business Machines Corporation

Inventor： Dallas Lea ,  Yann Mignot ,  Marc A. Bergendahl ,  Alex Joseph Varghese ,  Sean Teehan ,  Andrew M. Greene ,  Matthew T. Shoudy

IPC: H04L9/32 ,  H03K3/03 ,  H03H7/06 ,  H03H7/01 ,  H03K3/037

CPC classification number: H04L9/3278 ,  H03K3/0315 ,  H03H7/06 ,  H03H7/0161 ,  H03K3/037

Abstract: A physical unclonable function (PUF) device includes a ring oscillator, a plurality of band-pass filters, a demultiplexer, and a latch. The ring oscillator generates a frequency signal. Each passive band-pass filter performs filtering on the frequency signal to pass the frequency signal or block the frequency signal. The demultiplexer receives a set of challenge bits and delivers the frequency signal to a selected passive band-pass filter among the plurality of passive band-passed filters based on the challenge bit. The latch outputs a response bit in response to the filtering performed by the selected passive band-pass filter.

公开(公告)号：US20210351082A1

公开(公告)日：2021-11-11

申请号：US17382442

申请日：2021-07-22

Applicant: International Business Machines Corporation

Inventor： Eric Miller ,  Marc A. Bergendahl ,  Kangguo Cheng ,  Sean Teehan ,  John Sporre

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/66 ,  H01L29/10 ,  H01L21/02 ,  H01L29/78 ,  H01L27/088

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

公开(公告)号：US20210104440A1

公开(公告)日：2021-04-08

申请号：US16590512

申请日：2019-10-02

Applicant: International Business Machines Corporation

Inventor： ERIC MILLER ,  Marc A. Bergendahl ,  Kangguo Cheng ,  Sean Teehan ,  John Sporre

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L21/02 ,  H01L29/78 ,  H01L27/088

Abstract: Embodiments of the present invention are directed to fabrication method and resulting structures for vertical tunneling field effect transistors (VFETs) having a dual liner bottom spacer. In a non-limiting embodiment of the invention, a first liner is formed on a top surface of a source or drain (S/D) region and sidewalls of a semiconductor fin. Portions of a spacer are removed to expose a first region and a second region of the first liner. The first region of the first liner is directly on the S/D region and the second region is over the semiconductor fin. A second liner is formed on the first liner. A first portion of the second liner is formed by selectively depositing dielectric material on the exposed first region and exposed second region of the first liner. The first liner and the second liner collectively define the dual liner bottom spacer.

公开(公告)号：US10937810B2

公开(公告)日：2021-03-02

申请号：US16541429

申请日：2019-08-15

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84 ,  H01L29/78

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US10446452B2

公开(公告)日：2019-10-15

申请号：US15489303

申请日：2017-04-17

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Ryan O. Jung ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/84 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/308 ,  H01L21/66 ,  H01L27/12 ,  H01L21/8234

Abstract: A method and structure to enable reliable dielectric spacer endpoint detection by utilizing a sacrificial spacer fin are provided. The sacrificial spacer fin that is employed has a same pitch as the pitch of each semiconductor fin and the same height as the dielectric spacers on the sidewalls of each semiconductor fin. Exposed portions of the sacrificial spacer fin are removed simultaneously during a dielectric spacer reactive ion etch (RIE). The presence of the sacrificial spacer fin improves the endpoint detection of the spacer RIE and increases the endpoint signal intensity.

公开(公告)号：US10438972B2

公开(公告)日：2019-10-08

申请号：US15263005

申请日：2016-09-12

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Gauri Karve ,  Fee Li Lie ,  Eric R. Miller ,  John R. Sporre ,  Sean Teehan

IPC: H01L27/12 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L21/84

Abstract: Sub-fin removal techniques for SOI like isolation in finFET devices are provided. In one aspect, a method for forming a finFET device includes: etching partial fins in a substrate, wherein the partial fins include top portions of fins of the finFET device; forming a bi-layer spacer on the top portions of the fins; complete etching of the fins in the substrate to form bottom portions of the fins of the finFET device; depositing an insulator between the fins; recessing the insulator enough to expose a region of the fins not covered by the bi-layer spacer; removing the exposed region of the fins to create a gap between the top and bottom portions of the fins; filling the gap with additional insulator. A method for forming a finFET device is also provided where placement of the fin spacer occurs after (rather than before) insulator deposition. A finFET device is also provided.

公开(公告)号：US10242882B2

公开(公告)日：2019-03-26

申请号：US15620806

申请日：2017-06-12

Applicant: International Business Machines Corporation

Inventor： Zhenxing Bi ,  Donald F. Canaperi ,  Thamarai S. Devarajan ,  Sean Teehan

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/3105

Abstract: Methods are provided to implement a cyclic etch process to remove oxide layers for semiconductor device fabrication. For example, a method comprises performing a cyclic etch process to incrementally etch an oxide layer, wherein the cyclic etch process comprises sequentially performing at least two instances of an etch cycle. The etch cycle comprises performing an etch process to partially etch a portion of the oxide layer using an etch chemistry and environment which is configured to etch down the oxide layer at an etch rate of about 25 angstroms/minute or less, and performing a thermal treatment to remove by-products of the etch process. The cyclic etch process can be implemented as part of a replacement metal gate process to remove a dummy gate oxide layer of a dummy gate structure as part of, e.g., a FinFET semiconductor fabrication process flow.

公开(公告)号：US10074730B2

公开(公告)日：2018-09-11

申请号：US15008615

申请日：2016-01-28

Applicant: International Business Machines Corporation

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  Fee Li Lie ,  Eric R. Miller ,  Jeffrey C. Shearer ,  John R. Sporre ,  Sean Teehan

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/306 ,  H01L29/16 ,  H01L29/78 ,  H01L29/40 ,  H01L29/775

CPC classification number: H01L29/66742 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78651 ,  H01L29/78696 ,  H01L2029/7858

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

公开(公告)号：US10026615B2

公开(公告)日：2018-07-17

申请号：US15153226

申请日：2016-05-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/033 ,  H01L29/66

Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using an angled deposition process. A second sidewall of one or more of the plurality of mandrels is masked. Second spacers are formed on a second sidewall of all unmasked mandrels. The second sidewall of the one or more of the plurality of mandrels is unmasked. The mandrels are etched away. Fins are formed from a substrate using the first and second spacers as a mask.

公开(公告)号：US20180190491A1

公开(公告)日：2018-07-05

申请号：US15908166

申请日：2018-02-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Marc A. Bergendahl ,  Kangguo Cheng ,  John R. Sporre ,  Sean Teehan

IPC: H01L21/033 ,  H01L29/66

CPC classification number: H01L21/0337 ,  H01L21/3086 ,  H01L21/32105 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/66795

Abstract: Methods of forming semiconductor fins include forming first spacers on a first sidewall of each of a plurality of mandrels using a directional deposition process. A finless region is masked by forming a mask on a second sidewall of one or more of the plurality of mandrels. Second spacers are formed on a second sidewall of unmasked mandrels using a directional deposition process. The finless region is unmasked and each of the plurality of mandrels is etched away. Fins are formed from a substrate using the first and second spacers as a mask, such that no fins are formed in the finless region.