公开(公告)号：US20170077149A1

公开(公告)日：2017-03-16

申请号：US15341041

申请日：2016-11-02

Applicant: Japan Display Inc.

Inventor： Norihiro UEMURA ,  lsao SUZUMURA ,  Hidekazu MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L27/12 ,  H01L29/417 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/1368 ,  G02F1/1362 ,  H01L29/786 ,  H01L27/32

CPC classification number: H01L27/1225 ,  G02F1/133345 ,  G02F1/134309 ,  G02F1/136209 ,  G02F1/1368 ,  G02F2001/133302 ,  G02F2001/134372 ,  H01L27/124 ,  H01L27/3272 ,  H01L27/3276 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided are a reliable high performance thin film transistor and a reliable high performance display device. The display device has: a gate electrode which is formed on a substrate; a gate insulating film which is formed to cover the substrate and the gate electrode; an oxide semiconductor layer which is formed on the gate electrode through the gate insulating film; a channel protective layer which is in contact with the oxide semiconductor layer and formed on the oxide semiconductor layer; and source/drain electrodes which are electrically connected to the oxide semiconductor layer and formed to cover the oxide semiconductor layer. A metal oxide layer is formed on an upper part of the channel protective layer. The source/drain electrodes are formed to be divided apart on the channel protective layer and the metal oxide layer.

Abstract translation: 提供可靠的高性能薄膜晶体管和可靠的高性能显示器件。 显示装置具有形成在基板上的栅电极; 形成为覆盖基板和栅电极的栅极绝缘膜; 通过栅极绝缘膜形成在栅电极上的氧化物半导体层; 沟道保护层，其与所述氧化物半导体层接触并形成在所述氧化物半导体层上; 以及与氧化物半导体层电连接并形成为覆盖氧化物半导体层的源极/漏极。 金属氧化物层形成在沟道保护层的上部。 源极/漏极形成为在沟道保护层和金属氧化物层上分开。

公开(公告)号：US20160209719A1

公开(公告)日：2016-07-21

申请号：US14990201

申请日：2016-01-07

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  lsao SUZUMURA

IPC: G02F1/1362 ,  H01L29/786 ,  G02F1/1368 ,  H01L27/12

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F2001/136218 ,  G02F2001/13685 ,  G02F2202/10 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/78633 ,  H01L29/7869

Abstract: According to one embodiment, a display device includes an insulating substrate, a thin-film transistor including a semiconductor layer formed on a layer above the insulating substrate, a gate electrode which at least partly overlaps the semiconductor layer, and a first electrode and a second electrode which are electrically connected to the semiconductor layer, and a light shielding layer formed between the thin-film transistor and the insulating substrate to at least partly overlap the semiconductor layer, the light shielding layer electrically connected to the gate electrode.

Abstract translation: 根据一个实施例，显示装置包括绝缘基板，薄膜晶体管，其包括形成在绝缘基板上的层上的半导体层，至少部分地与半导体层重叠的栅电极，以及第一电极和第二电极 与半导体层电连接的电极，以及形成在薄膜晶体管和绝缘基板之间的遮光层，至少部分地与半导体层重叠，遮光层与栅电极电连接。

公开(公告)号：US20240402552A1

公开(公告)日：2024-12-05

申请号：US18798914

申请日：2024-08-09

Applicant: Japan Display Inc.

Inventor： Toshihide JINNAI ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  lsao SUZUMURA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/786 ,  H10K59/131

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor is covered by a first insulating film, a first drain electrode is connected to the oxide semiconductor via a first through hole formed in the first insulating film, a first source electrode is connected to the oxide semiconductor via second through hole formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode and the first source electrode, a drain wiring connects to the first drain electrode via a third through hole formed in the second insulating film, a source wiring is connected to the first source electrode via a fourth through hole formed in the second insulating film.

公开(公告)号：US20200259020A1

公开(公告)日：2020-08-13

申请号：US16785662

申请日：2020-02-10

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Tomoyuki ITO ,  Toshihide JINNAI ,  lsao SUZUMURA ,  Akihiro HANADA ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

公开(公告)号：US20160211177A1

公开(公告)日：2016-07-21

申请号：US14996323

申请日：2016-01-15

Applicant: Japan Display Inc.

Inventor： lsao SUZUMURA ,  Arichika ISHIDA ,  Hidekazu MIYAKE ,  Hiroto MIYAKE ,  Yohei YAMAGUCHI

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/417 ,  H01L21/02

CPC classification number: H01L21/76895 ,  H01L21/022 ,  H01L21/32136 ,  H01L21/465 ,  H01L21/78 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/7869

Abstract: According to one embodiment, a method of manufacturing a thin-film transistor includes forming a semiconductor layer on a gate electrode with an insulating layer 12 being interposed, forming interconnect formation layers on the semiconductor layer, forming a plurality of interconnects and electrodes by patterning the interconnect formation layers through etching, patterning the semiconductor layer in an island shape through etching after forming the electrodes, exposing a channel region of the semiconductor layer by etching a part of the electrodes on the semiconductor layer, and forming a protective layer so as to overlap the interconnects, the electrodes and the semiconductor layer having the island shape.

Abstract translation: 根据一个实施例，制造薄膜晶体管的方法包括在绝缘层12插入的栅电极上形成半导体层，在半导体层上形成互连形成层，通过图案化形成多个互连和电极 通过蚀刻进行互连形成层，在形成电极之后通过蚀刻将半导体层图案化为岛状，通过蚀刻半导体层上的一部分电极来暴露半导体层的沟道区域，并形成保护层以重叠 互连，电极和具有岛状的半导体层。

公开(公告)号：US20230317853A1

公开(公告)日：2023-10-05

申请号：US18328788

申请日：2023-06-05

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Tomoyuki ITO ,  Toshihide JINNAI ,  lsao SUZUMURA ,  Akihiro HANADA ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/426 ,  H01L21/4757 ,  H01L21/4763 ,  H01L29/66

CPC classification number: H01L29/78627 ,  H01L27/124 ,  H01L27/1251 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78633 ,  H01L29/78675 ,  H01L29/7869 ,  H01L27/127 ,  H01L21/02178 ,  H01L21/02565 ,  H01L21/426 ,  H01L21/47573 ,  H01L21/47635 ,  H01L29/66969 ,  H01L27/1225 ,  G02F1/1368

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

公开(公告)号：US20230074655A1

公开(公告)日：2023-03-09

申请号：US17987887

申请日：2022-11-16

Applicant: Japan Display Inc.

Inventor： Toshihide JINNAI ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  lsao SUZUMURA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  H01L27/32

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.

公开(公告)号：US20220029026A1

公开(公告)日：2022-01-27

申请号：US17499908

申请日：2021-10-13

Applicant: Japan Display Inc.

Inventor： Hajime WATAKABE ,  Tomoyuki ITO ,  Toshihide JINNAI ,  lsao SUZUMURA ,  Akihiro HANADA ,  Ryo ONODERA

IPC: H01L29/786 ,  H01L21/02 ,  H01L27/12 ,  H01L29/66 ,  H01L21/4763 ,  H01L29/49 ,  H01L21/426 ,  H01L29/423 ,  H01L29/24 ,  H01L21/4757 ,  G02F1/1368

Abstract: A semiconductor device includes thin film transistors each having an oxide semiconductor. The oxide semiconductor has a channel region, a drain region, a source region, and low concentration regions which are lower in impurity concentration than the drain region and the source region. The low concentration regions are located between the channel region and the drain region, and between the channel region and the source region. Each of the thin film transistors has a gate insulating film on the channel region and the low concentration regions, an aluminum oxide film on a first part of the gate insulating film, the first part being located on the channel region, and a gate electrode on the aluminum oxide film and a second part of the gate insulating film, the second part being located on the low concentration regions.

公开(公告)号：US20200264484A1

公开(公告)日：2020-08-20

申请号：US16787054

申请日：2020-02-11

Applicant: Japan Display Inc.

Inventor： Toshihide JINNAI ,  Hajime WATAKABE ,  Akihiro HANADA ,  Ryo ONODERA ,  lsao SUZUMURA

IPC: G02F1/1362 ,  G02F1/1368 ,  H01L27/32 ,  H01L29/786 ,  H01L27/12

Abstract: A display device including a substrate having a first TFT of an oxide semiconductor and a second TFT of a polysilicon semiconductor comprising: the oxide semiconductor 109 is covered by a first insulating film, a first drain electrode 110 is connected to the oxide semiconductor 109 via a first through hole 132 formed in the first insulating film, a first source electrode 111 is connected to the oxide semiconductor 109 via second through hole 133 formed in the first insulating film in the first TFT, a second insulating film is formed covering the first drain electrode 110 and the first source electrode 111, a drain wiring connects 12 to the first drain electrode 110 via a third through hole 130 formed in the second insulating film, a source wiring 122 is connected to the first source electrode 111 via a fourth through hole 131 formed in the second insulating film.

公开(公告)号：US20180294286A1

公开(公告)日：2018-10-11

申请号：US16004546

申请日：2018-06-11

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  lsao SUZUMURA ,  Hidekazu MIYAKE

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/32 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: H01L27/1288 ,  G02F1/136227 ,  G02F1/1368 ,  G02F2201/123 ,  G02F2202/104 ,  H01L27/1225 ,  H01L27/1229 ,  H01L27/1233 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127 ,  H01L27/3262 ,  H01L27/3276 ,  H01L29/78693

Abstract: The invention allows formation of LTPS TFTs and TAOS TFTs on the same substrate. The invention provides a display device including a substrate having a display area in which pixels are formed. The pixels include a first TFT made of a TAOS. The drain of the first TFT is formed of first LTPS 112. The source of the first TFT is formed of second LTPS 113. The first LTPS 112 is connected to a first electrode 106 via a first through-hole 108 formed in an insulating film 105 covering the first TFT. The second LTPS 113 is connected to a second electrode 107 via a second through-hole 108 formed in the insulating film 105 covering the first TFT.