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    Reactive ion etching buffer mask
    2.
    发明授权
    Reactive ion etching buffer mask 失效
    反应离子蚀刻缓冲掩模

    公开(公告)号：US5118384A

    公开(公告)日：1992-06-02

    申请号：US807960

    申请日：1991-12-10

    申请人： David L. Harmon ,  Michael L. Kerbaugh ,  Nancy T. Pascoe ,  John F. Rembetski

    发明人： David L. Harmon ,  Michael L. Kerbaugh ,  Nancy T. Pascoe ,  John F. Rembetski

    IPC分类号： H01L21/3065 ,  H01L21/308

    CPC分类号： H01L21/3065 ,  H01L21/3085

    摘要： An improved mask and method of forming a deep and uniform width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material. Thus, only those ions which are directed essentially normal to the underlying substrate perform the trench etching. This allows the trench to have essentially straight side walls and to be of essentially uniform width.

    摘要翻译： 公开了一种在衬底中形成深而均匀的宽度沟槽的改进的掩模和方法，并且所得到的结构被公开。 诸如硅的衬底材料在其上沉积有第一层牺牲材料作为蚀刻掩模的第一组分，牺牲材料是诸如多晶硅的材料，其被蚀刻或吸收相同的离子，其反应离子蚀刻衬底。 作为蚀刻掩模的第二组分，第二层材料，其抵抗反应离子蚀刻，例如二氧化硅，沉积在第一材料层上。 二氧化硅以形成在衬底中的沟槽的形式构图。 然后层状多晶硅材料被反应离子蚀刻，并且反应离子蚀刻继续在硅衬底中形成沟槽。 多晶硅充当被二氧化硅反射的任何离子蚀刻的牺牲材料，或以一定角度被引导使得它们撞击多晶硅材料层。 因此，仅基本上垂直于下面的衬底的那些离子执行沟槽蚀刻。 这允许沟槽具有基本上直的侧壁并且具有基本均匀的宽度。

    Reactive ion etching buffer mask
    3.
    发明授权
    Reactive ion etching buffer mask 失效
    反应离子蚀刻缓冲掩模

    公开(公告)号：US5298790A

    公开(公告)日：1994-03-29

    申请号：US958462

    申请日：1992-10-08

    申请人： David L. Harmon ,  Michael L. Kerbaugh ,  Nancy T. Pascoe ,  John F. Rembetski

    发明人： David L. Harmon ,  Michael L. Kerbaugh ,  Nancy T. Pascoe ,  John F. Rembetski

    IPC分类号： H01L21/3065 ,  H01L21/308 ,  H01L29/68 ,  H01L29/04 ,  H01L29/06

    CPC分类号： H01L21/3085 ,  H01L21/3065

    摘要： An improved mask and method of forming a deep and width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material. Thus, only those ions which are directed essentially normal to the underlying substrate perform the trench etching. This allows the trench to have essentially straight side walls and to be of essentially uniform width.

    摘要翻译： 公开了一种在衬底中形成深和宽沟槽的改进掩模和方法，并且所得到的结构被公开。 诸如硅的衬底材料在其上沉积有第一层牺牲材料作为蚀刻掩模的第一组分，牺牲材料是诸如多晶硅的材料，其被蚀刻或吸收相同的离子，其反应离子蚀刻衬底。 作为蚀刻掩模的第二组分，第二层材料，其抵抗反应离子蚀刻，例如二氧化硅，沉积在第一材料层上。 二氧化硅以形成在衬底中的沟槽的形式构图。 然后层状多晶硅材料被反应离子蚀刻，并且反应离子蚀刻继续在硅衬底中形成沟槽。 多晶硅充当被二氧化硅反射的任何离子蚀刻的牺牲材料，或以一定角度被引导使得它们撞击多晶硅材料层。 因此，仅基本上垂直于下面的衬底的那些离子执行沟槽蚀刻。 这允许沟槽具有基本上直的侧壁并且具有基本均匀的宽度。

    Forming wide dielectric-filled isolation trenches in semi-conductors
    4.
    发明授权
    Forming wide dielectric-filled isolation trenches in semi-conductors 失效
    在半导体中形成宽电介质填充的隔离沟槽

    公开(公告)号：US5173439A

    公开(公告)日：1992-12-22

    申请号：US679568

    申请日：1991-04-02

    申请人： Somanath Dash ,  Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Machesney ,  Nitin B. Parekh

    发明人： Somanath Dash ,  Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Machesney ,  Nitin B. Parekh

    IPC分类号： H01L21/3105 ,  H01L21/311 ,  H01L21/762

    CPC分类号： H01L21/02063 ,  H01L21/3105 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/76229

    摘要： A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrate. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.

    摘要翻译： 提供了一种在半导体衬底中形成平坦化介质填充的宽浅沟槽的方法。 将诸如Si 3 N 4的蚀刻停止层沉积到半导体衬底上，并且通过常规RIE通过Si 3 N 4形成宽的沟槽进入衬底。 包括沟槽的衬底的表面在其上形成符合衬底表面的SiO 2涂层。 将诸如多晶硅的耐蚀刻材料层沉积到SiO 2材料上。 然后通过化学机械抛光去除沟槽宽度外的多晶硅，以在下面暴露出SiO 2，同时在覆盖有多晶硅的沟槽上留下SiO 2。 然后将暴露的SiO 2 RIE蚀刻到Si 3 N 4上，在每个沟槽上留下带有耐蚀刻多晶硅的SiO 2塞。 然后通过机械抛光除去Si 3 N 4，从而在衬底的顶部提供SiO 2和Si 3 N 4的平坦化上表面。 本发明还可用于在具有填充有导电材料的沟槽的衬底上形成平坦化表面。

    Forming wide dielectric-filled planarized isolation trenches in semiconductors
    9.
    发明授权
    Forming wide dielectric-filled planarized isolation trenches in semiconductors 失效
    在半导体中形成广泛的电介质平面隔离开关

    公开(公告)号：US5006482A

    公开(公告)日：1991-04-09

    申请号：US427153

    申请日：1989-10-25

    申请人： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Macheeney

    发明人： Michael L. Kerbaugh ,  Charles W. Koburger, III ,  Brian J. Macheeney

    IPC分类号： H01L21/76 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

    CPC分类号： H01L21/02063 ,  H01L21/31053 ,  H01L21/31116 ,  H01L21/76229

    摘要： A method of forming a planarized dielectric filled wide shallow trench in a semi-conductor substrate is provided. A layer of etch stop such as Si.sub.3 N.sub.4 is deposited onto the semi-conductor substrate, and wide trenches are formed through the Si.sub.3 N.sub.4 into the substrate by conventional RIE. The surface of the substrate including the trenches have formed thereon a SiO.sub.2 coating, conforming to the surface of the substrater. A layer of etch resistant material such as polysilicon is deposited onto the SiO.sub.2 material. The polysilicon outside the width of the trenches is then removed by chemical-mechanical polishing to expose the SiO.sub.2 there below, while leaving the SiO.sub.2 above the trenches covered with polysilicon. The exposed SiO.sub.2 is then RIE etched down to the Si.sub.3 N.sub.4, leaving a plug of SiO.sub.2 capped with the etch resistant polysilicon over each trench. These plugs are then removed by mechanical polishing down to the Si.sub.3 N.sub.4, to provide a planarized upper surface of SiO.sub.2 and Si.sub.3 N.sub.4 on the top of the substrate. The invention also is useful in forming planarized surfaces on substrates having trenches filled with conductive material.