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    Process of making a microcavity structure and applications thereof
    1.
    发明授权
    Process of making a microcavity structure and applications thereof 失效
    制造微腔结构的方法及其应用

    公开(公告)号：US5773361A

    公开(公告)日：1998-06-30

    申请号：US744473

    申请日：1996-11-06

    申请人： John Edward Cronin ,  Anthony Kendall Stamper

    发明人： John Edward Cronin ,  Anthony Kendall Stamper

    IPC分类号： H01L21/768 ,  H01L21/88 ,  H01L21/94

    CPC分类号： H01L21/76828 ,  H01L21/7682 ,  H01L21/76897

    摘要： A microcavity structure and a method for forming an integrated circuit device including a microcavity structure is disclosed. This invention includes a layer or substrate having a topography such as a pair of raised features. A void forming material, such as a Boro-Phosphorus Silicate Glass (BPSG) is deposited on the substrate such that a void is formed therein. A pinning material having a relatively greater density than the void forming material is deposited over the void forming material. The materials are then annealed by a process such as Rapid Thermal Anneal (RTA). The materials are then polished, by for example, Chemical Mechanical Polishing (CMP) to expose the top of the void. The void is then etched using an anisotropic etch, such as Reactive Ion Etch (RIE) to remove the void forming material. The method may be used to provide self-aligned contact vias.

    摘要翻译： 公开了一种微腔结构和形成包括微​​腔结构的集成电路器件的方法。 本发明包括具有诸如一对凸起特征的形貌的层或衬底。 在基板上沉积诸如硼磷硅酸盐玻璃（BPSG）的空隙形成材料，使得其中形成空隙。 在空隙形成材料上沉积具有比空隙形成材料更大密度的钉扎材料。 然后通过诸如快速热退火（RTA）的工艺对材料进行退火。 然后通过例如化学机械抛光（CMP）抛光材料以暴露空隙的顶部。 然后使用各向异性蚀刻（例如反应离子蚀刻（RIE））蚀刻空隙以除去空隙形成材料。 该方法可以用于提供自对准接触孔。

    Tapered via and MIM capacitor
    4.
    发明授权
    Tapered via and MIM capacitor 有权
    锥形通孔和MIM电容器

    公开(公告)号：US08649153B2

    公开(公告)日：2014-02-11

    申请号：US13096850

    申请日：2011-04-28

    申请人： James Stuart Dunn ,  Zhong-Xiang He ,  Anthony Kendall Stamper

    发明人： James Stuart Dunn ,  Zhong-Xiang He ,  Anthony Kendall Stamper

    IPC分类号： H01G4/30

    CPC分类号： H01L28/40 ,  H01G4/228 ,  H01G4/33

    摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.

    摘要翻译： 描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。 描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。

    Fuse and pad stress relief
    8.
    发明授权
    Fuse and pad stress relief 有权
    保险丝和垫的应力消除

    公开(公告)号：US08137791B2

    公开(公告)日：2012-03-20

    申请号：US11954557

    申请日：2007-12-12

    申请人： Felix Patrick Anderson ,  Jeffrey Peter Gambino ,  Thomas Leddy McDevitt ,  Anthony Kendall Stamper

    发明人： Felix Patrick Anderson ,  Jeffrey Peter Gambino ,  Thomas Leddy McDevitt ,  Anthony Kendall Stamper

    IPC分类号： H01L21/4763 ,  H01L21/44 ,  H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  B32B15/04 ,  B32B9/06

    CPC分类号： H01L21/76885 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/522 ,  H01L23/5254 ,  H01L2224/16225 ,  Y10T428/2462

    摘要： A structure and method of forming the structure. At least one copper wire is formed within a first dielectric layer of a substrate. The top surface of each copper wire and of the first dielectric layer are essentially coplanar. A recess is formed in the first dielectric layer from the top surface of each copper wire to a recess depth less than a thickness of each copper wire within the first dielectric layer such that the recess surrounds a perimeter surface of each copper wire. A capping layer, which is a copper diffusion barrier, is formed in the recess and on the top surface of each copper wire and on the first dielectric layer. A second dielectric layer is formed on the capping layer. The recess depth has a magnitude sufficient to prevent a lateral fail of the capping layer during packaging and/or operation of the substrate.

    摘要翻译： 形成结构的结构和方法。 在衬底的第一介电层内形成至少一根铜线。 每个铜线和第一介电层的顶表面基本上是共面的。 在第一电介质层中，从每根铜线的顶表面形成凹槽，凹陷深度小于第一介电层内的每根铜线的厚度，使得该凹槽围绕每根铜线的周边表面。 作为铜扩散阻挡层的覆盖层形成在每个铜线的凹部和顶面以及第一电介质层上。 在覆盖层上形成第二电介质层。 凹陷深度具有足以防止在封装和/或操作衬底期间封盖层的横向失效的量级。

    THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE
    10.
    发明申请
    THROUGH SUBSTRATE VIA INCLUDING VARIABLE SIDEWALL PROFILE 有权
    通过基础包括可变的平台轮廓

    公开(公告)号：US20110068477A1

    公开(公告)日：2011-03-24

    申请号：US12955429

    申请日：2010-11-29

    申请人： Edward Crandal Cooney, III ,  Peter James Lindgren ,  Doreen Jane Ossenkop ,  Anthony Kendall Stamper

    发明人： Edward Crandal Cooney, III ,  Peter James Lindgren ,  Doreen Jane Ossenkop ,  Anthony Kendall Stamper

    IPC分类号： H01L23/538 ,  H05K1/11

    CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A microelectronic structure, such as a semiconductor structure, and a method for fabricating the microelectronic structure, include an aperture within a substrate. Into the aperture is located and formed a via. The via may include a through substrate via. The aperture includes, progressing sequentially contiguously at least partially through the substrate: (1) a first comparatively wide region at a surface of the substrate; (2) a constricted region contiguous with the first comparatively wide region; (3) a second comparatively wide region contiguous with the constricted region; and (4) a tapered region contiguous with the second comparatively wide region. The structure of the aperture provides for ease in filling the aperture, as well as void isolation within the via that is filled into the aperture.

    摘要翻译： 诸如半导体结构的微电子结构和用于制造微电子结构的方法包括在衬底内的孔。 进入孔位于并形成通孔。 通孔可以包括通孔基板通孔。 所述孔包括，至少部分地依次连续地进行穿过所述基底：（1）在所述基底的表面处的第一相对较宽的区域; （2）与第一相对宽的区域相邻的收缩区域; （3）与收缩区域相邻的第二相对宽的区域; 和（4）与第二较宽区域相邻的锥形区域。 孔的结构提供了填充孔的容易性，以及填充到孔中的通孔内的空隙隔离。