利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.028 秒)

    Master glass having structure capable of preventing damage caused by static electricity
    3.
    发明授权
    Master glass having structure capable of preventing damage caused by static electricity 有权
    具有能够防止由静电引起的损坏的结构的主玻璃

    公开(公告)号：US08786173B2

    公开(公告)日：2014-07-22

    申请号：US12837354

    申请日：2010-07-15

    申请人： Jae-Yong Lee ,  Won-Kyu Kwak ,  Jae-Jung Kim ,  Tae-Jin Park ,  Dong-Young Sung

    发明人： Jae-Yong Lee ,  Won-Kyu Kwak ,  Jae-Jung Kim ,  Tae-Jin Park ,  Dong-Young Sung

    IPC分类号： H01L23/60 ,  H01L23/62

    CPC分类号： H05K1/0259 ,  H01L27/3223 ,  H01L51/56 ,  H05K1/0269 ,  H05K2201/0108 ,  H05K2201/10204 ,  H05K2203/173

    摘要： There is provided a master glass having a structure capable of preventing damage caused by static electricity. The master glass is a substrate on which a deposition process is experimentally performed by being experimentally loaded loading the master glass into a deposition apparatus before starting the deposition process of the substrate for electronic devices. In one embodiment, a master glass includes first conductive patterns and a second conductive pattern. The first conductive patterns are formed to correspond to a deposition pattern required in a substrate for electronic devices. The second conductive pattern electrically connects all the first conductive patterns to one another.

    摘要翻译： 提供了具有能够防止由静电引起的损坏的结构的主玻璃。 主玻璃是通过在开始用于电子设备的基板的沉积工艺之前通过实验负载将主玻璃加载到沉积设备中而实验沉积过程的基板。 在一个实施例中，主玻璃包括第一导电图案和第二导电图案。 形成第一导电图案以对应于用于电子设备的基板中所需的沉积图案。 第二导电图案将所有第一导电图案彼此电连接。

    Methods of manufacturing a capacitor and a semiconductor device
    7.
    发明申请
    Methods of manufacturing a capacitor and a semiconductor device 审中-公开
    制造电容器和半导体器件的方法

    公开(公告)号：US20060115954A1

    公开(公告)日：2006-06-01

    申请号：US11265937

    申请日：2005-11-03

    申请人： Woo-Seok Shim ,  Young-Wook Park ,  Jung-Hyeon Lee ,  Kwang-Sub Yoon ,  Chul-Ho Kim ,  Tae-Jin Park

    发明人： Woo-Seok Shim ,  Young-Wook Park ,  Jung-Hyeon Lee ,  Kwang-Sub Yoon ,  Chul-Ho Kim ,  Tae-Jin Park

    IPC分类号： H01L21/20 ,  H01L21/8242

    CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852

    摘要： In methods of manufacturing a capacitor and a semiconductor device, a mold layer is formed on a substrate having a contact plug. The mold layer includes an opening exposing the contact plug. A conductive layer is formed on the contact plug, an inner sidewall of the opening and the mold layer. A photoresist pattern is formed to substantially fill the opening. A cylindrical lower electrode is formed by partially removing the conductive layer. The mold layer is selectively removed while the photoresist pattern prevents damage to the lower electrode, the contact plug and the substrate. The photoresist pattern is removed, and then a dielectric layer and an upper electrode are sequentially formed on the lower electrode. Damage to the lower electrode and the contact plug are effectively prevented due to the presence of the photoresist pattern during selective removal of the mold layer.

    摘要翻译： 在制造电容器和半导体器件的方法中，在具有接触插塞的基板上形成模层。 模具层包括露出接触塞的开口。 在接触插塞，开口的内侧壁和模具层上形成导电层。 形成光致抗蚀剂图案以基本上填充开口。 通过部分去除导电层形成圆柱形下电极。 选择性地去除模具层，同时光刻胶图案防止损坏下部电极，接触插塞和基板。 去除光致抗蚀剂图案，然后在下电极上依次形成电介质层和上电极。 由于在选择性去除模具层期间存在光致抗蚀剂图案，因此有效地防止了下电极和接触插塞的损坏。

    Phase change memory devices and methods of manufacturing the same
    8.
    发明授权
    Phase change memory devices and methods of manufacturing the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US08824187B2

    公开(公告)日：2014-09-02

    申请号：US13487567

    申请日：2012-06-04

    申请人： Tae-Jin Park ,  Ki-Hoon Do ,  Myung-Jin Kang

    发明人： Tae-Jin Park ,  Ki-Hoon Do ,  Myung-Jin Kang

    IPC分类号： H01L21/782 ,  G11C11/21 ,  H01L27/10

    CPC分类号： H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1675

    摘要： A phase change memory device includes a plurality of word lines, a plurality of lower electrodes, and a plurality of phase change material patterns. The plurality of word lines extend in a first direction and the plurality of word lines are arranged along a second direction perpendicular to the first direction. The lower electrodes are on the word lines and the lower electrodes are arranged in a direction diagonal to the first direction by a first angle. Each of the plurality of phase change material patterns are on a corresponding one of the plurality of lower electrodes.

    摘要翻译： 相变存储器件包括多个字线，多个下电极和多个相变材料图案。 多个字线沿着第一方向延伸，并且多个字线沿着垂直于第一方向的第二方向布置。 下电极位于字线上，下电极沿与第一方向对角的方向排列第一角度。 多个相变材料图案中的每一个在多个下电极中的相应一个上。

    Method Of Aligning A Wafer Stage And Apparatus For Performing The Same
    9.
    发明申请
    Method Of Aligning A Wafer Stage And Apparatus For Performing The Same 有权
    对准晶片台的方法及其执行装置

    公开(公告)号：US20120092638A1

    公开(公告)日：2012-04-19

    申请号：US13221360

    申请日：2011-08-30

    申请人： Tae-Jin Park ,  Cheol-Hong Kim

    发明人： Tae-Jin Park ,  Cheol-Hong Kim

    IPC分类号： G03B27/58

    CPC分类号： G03B27/58 ,  G03B27/53 ,  G03F7/70775 ,  G03F9/7088

    摘要： In a method of aligning a wafer stage, the wafer stage may be moved in an X-axis direction. A first coordinate of the wafer stage may be measured from a first measurement position inclined to the X-axis. The wafer stage may be moved in a Y-axis direction. A second coordinate of the wafer stage may be measured from a second measurement position inclined to the Y-axis. Thus, a movement distance of the wafer stage may be increased, so that the interferometers may accurately measure the position of the wafer stage.

    摘要翻译： 在对准晶片台的方法中，晶片台可以在X轴方向上移动。 可以从倾斜于X轴的第一测量位置测量晶片台的第一坐标。 晶片载物台可沿Y轴方向移动。 可以从与Y轴倾斜的第二测量位置测量晶片台的第二坐标。 因此，可以增加晶片台的移动距离，使得干涉仪可以精确地测量晶片台的位置。

    Display device having set protection function upon generation of abnormal voltage
    10.
    发明授权
    Display device having set protection function upon generation of abnormal voltage 失效
    显示装置在产生异常电压时具有保护功能

    公开(公告)号：US5945793A

    公开(公告)日：1999-08-31

    申请号：US805334

    申请日：1997-02-24

    申请人： Tae-Jin Park ,  Ho-Jin Byun

    发明人： Tae-Jin Park ,  Ho-Jin Byun

    IPC分类号： H04N3/16 ,  G09G1/00 ,  G09G1/04 ,  H04N3/18 ,  H04N3/20

    CPC分类号： H04N3/20 ,  H04N3/18

    摘要： A display device having a set protecting function upon generation of an abnormal voltage includes a horizontal deflection circuit for providing a horizontal signal to a deflection yoke connector, a high voltage output circuit for supplying a high voltage to an anode in accordance with an oscillating signal applied from the horizontal deflection circuit, a power supply circuit for supplying power to the horizontal deflection circuit, and an abnormal voltage detector disposed between the deflection yoke connector, and the high voltage output circuit and the power supply circuit, for detecting whether the deflection yoke connector is connected and whether a part of the high voltage output circuit is damaged, to thereby control a power output of the power supply circuit in accordance with a detected result.

    摘要翻译： 在产生异常电压时具有设定保护功能的显示装置包括用于向偏转线圈连接器提供水平信号的水平偏转电路，用于根据所施加的振荡信号向阳极提供高电压的高压输出电路 来自水平偏转电路的用于向水平偏转电路供电的电源电路和设置在偏转线圈连接器与高压输出电路和电源电路之间的异常电压检测器，用于检测偏转线圈连接器 并且高压输出电路的一部分是否损坏，从而根据检测结果来控制电源电路的电力输出。