公开(公告)号：US20240282384A1

公开(公告)日：2024-08-22

申请号：US18612239

申请日：2024-03-21

Applicant: Kioxia Corporation

Inventor： Takashi MAEDA

IPC: G11C16/16 ,  G11C5/14 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/30 ,  H02J50/12 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H02J50/12 ,  H10B43/27 ,  H10B43/35 ,  G11C5/145 ,  G11C16/30 ,  H02J2310/48

Abstract: When selectively erasing one sub-block, a control circuit applies, in a first sub-block, a first voltage to bit lines and a source line, and applies a second voltage smaller than the first voltage to the word lines. Then, the control circuit applies a third voltage lower than the first voltage by a certain value to a drain-side select gate line and a source-side select gate line, thereby performing the erase operation in the first sub-block. The control circuit applies, in a second sub-block existing in an identical memory block to the 10 selected sub-block, a fourth voltage substantially identical to the first voltage to the drain side select gate line and the source side select gate line, thereby not performing the erase operation in the second sub-block.

公开(公告)号：US20230297245A1

公开(公告)日：2023-09-21

申请号：US17899974

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Rieko FUNATSUKI ,  Takashi MAEDA ,  Sumiko DOMAE ,  Kazutaka IKEGAMI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659 ,  G06F3/0653

Abstract: A semiconductor memory device includes a semiconductor pillar including first and second memory cells electrically connected in series and formed on opposite sides of the semiconductor pillar, first word lines connected to the first memory cells, respectively, and second word lines connected to the second memory cells, respectively. A verify operation includes a channel clean operation for supplying a reference voltage to a semiconductor channel shared by the first and second memory cells followed by at least first and second sense operation for determining whether a threshold voltage of a target memory cell has reached first and second threshold voltage states, respectively, then a second channel clean operation for supplying the reference voltage to the semiconductor channel, and then at least a third sense operation for determining whether the threshold voltage of the target memory cell has reached a third threshold voltage state.

公开(公告)号：US20230078441A1

公开(公告)日：2023-03-16

申请号：US17689182

申请日：2022-03-08

Applicant: Kioxia Corporation

Inventor： Reiko SUMI ,  Takashi MAEDA ,  Hidehiro SHIGA

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: A semiconductor memory device of embodiments includes that in a write operation, the driver applies a first voltage to the first select gate line, applies a second voltage lower than the first voltage to the second select gate line, applies a third voltage equal to or higher than the first voltage to the first dummy word line on an uppermost layer, applies a fourth voltage different from the third voltage and higher than the second voltage to the second dummy word line on an uppermost layer, applies a fifth voltage equal to or higher than the third voltage to the first dummy word line on a lowermost layer, and applies a sixth voltage different from the fifth voltage and equal to or higher than the fourth voltage to the second dummy word line on a lowermost layer.

公开(公告)号：US20230074030A1

公开(公告)日：2023-03-09

申请号：US17984959

申请日：2022-11-10

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO ,  Takashi MAEDA ,  Masumi SAITOH ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US20220180942A1

公开(公告)日：2022-06-09

申请号：US17458059

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Kazutaka IKEGAMI ,  Hidehiro SHIGA ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Takayuki MIYAZAKI

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/20 ,  G11C16/30

Abstract: A semiconductor storage device includes a semiconductor pillar, a first string having first memory cells connected in series, first word lines connected to the first memory cells, a second string having second memory cells connected in series, and second word lines connected to the second memory cells. Each of the first memory cells faces, and shares a channel in the semiconductor pillar with, one of the second memory cells. When reading data of the k-th first memory cell, a voltage of the first word line connected to the k-th first memory cell reaches a first voltage at a first timing, and a voltage of the second word line connected to at least one of the second memory cells other than the k-th second memory cell in the second string facing the k-th first memory cell reaches the first voltage at a second timing that is later than the first timing.

公开(公告)号：US20210280257A1

公开(公告)日：2021-09-09

申请号：US17009376

申请日：2020-09-01

Applicant: KIOXIA CORPORATION

Inventor： Hidehiro SHIGA ,  Takashi MAEDA

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/24 ,  G11C16/08 ,  G11C16/04 ,  G11C16/30

Abstract: A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.

公开(公告)号：US20240046995A1

公开(公告)日：2024-02-08

申请号：US18176507

申请日：2023-03-01

Applicant: Kioxia Corporation

Inventor： Kyosuke SANO ,  Kazutaka IKEGAMI ,  Takashi MAEDA

IPC: G11C16/14 ,  G11C16/34 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/14 ,  G11C16/3459 ,  G11C16/08 ,  G11C16/26 ,  G11C16/0483

Abstract: A semiconductor memory device includes a first memory pillar and a sequencer. The first memory pillar is sandwiched between a first word line and a second word line, sandwiched between a third word line and a fourth word line, sandwiched between a fifth word line and a sixth word line, includes a first memory cell facing the first word line, a second memory cell facing the second word line, a third memory cell facing the third word line, a fourth memory cell facing the fourth word line, a fifth memory cell facing the fifth word line and a sixth memory cell facing the sixth word line. The sequencer executes an erase operation on the first to sixth memory cells to enable execution of a primary write operation for the first memory cell and a primary write operation for the second memory cell at different timings.

公开(公告)号：US20230122500A1

公开(公告)日：2023-04-20

申请号：US17930300

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Tsuneo INABA ,  Keisuke NAKATSUKA ,  Takashi MAEDA

IPC: H01L27/11573 ,  H01L27/1157 ,  H01L27/1158 ,  G11C5/06

Abstract: According to one embodiment, in a semiconductor memory device, a gate electrode of a first PMOS transistor and a gate electrode of a first NMOS transistor are commonly connected, and a first contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with an isolation portion when viewed in a third direction perpendicular to a first direction and a second direction. A gate electrode of a second PMOS transistor and a gate electrode of a second NMOS transistor are commonly connected, and a second contact plug is connected to the commonly-connected gate electrodes to at least partly overlap with the isolation portion when viewed in the third direction.

公开(公告)号：US20220093152A1

公开(公告)日：2022-03-24

申请号：US17201114

申请日：2021-03-15

Applicant: Kioxia Corporation

Inventor： Reika TANAKA ,  Masumi SAITOH ,  Takashi MAEDA ,  Rieko FUNATSUKI ,  Hidehiro SHIGA

IPC: G11C11/22 ,  H01L27/11597

Abstract: According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.

公开(公告)号：US20210296298A1

公开(公告)日：2021-09-23

申请号：US17005535

申请日：2020-08-28

Applicant: KIOXIA CORPORATION

Inventor： Tomoya SANUKI ,  Keisuke NAKATSUKA ,  Hiroshi MAEJIMA ,  Kenichiro YOSHII ,  Takashi MAEDA ,  Hideo WADA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.