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公开(公告)号：US10014291B2
公开(公告)日：2018-07-03
申请号：US13760496
申请日：2013-02-06
IPC分类号： H01L29/15 , H01L27/06 , H01L21/8258 , H01L27/085 , H01L21/265
CPC分类号： H01L27/0617 , H01L21/26506 , H01L21/8258 , H01L27/085 , H01L2924/0002 , H01L2924/00
摘要： A silicon substrate with a GaN-based device and a Si-based device on the silicon substrate is provided. The silicon substrate includes the GaN-based device on a SiC crystalline region. The SiC crystalline region is formed in the silicon substrate. The silicon substrate also includes the Si-based device on a silicon region, and the silicon region is next to the SiC crystalline region on the silicon substrate.
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2.发明授权Mechanism of forming SiC crystalline on Si substrates to allow integration of GaN and Si electronics 有权在Si衬底上形成SiC晶体以允许GaN和Si电子器件集成的机理公开(公告)号：US08389348B2
公开(公告)日：2013-03-05
申请号：US12881505
申请日：2010-09-14
IPC分类号： H01L21/338
CPC分类号： H01L27/0617 , H01L21/26506 , H01L21/8258 , H01L27/085 , H01L2924/0002 , H01L2924/00
摘要： The mechanisms of forming SiC crystalline regions on Si substrate described above enable formation and integration of GaN-based devices and Si-based devices on a same substrate. The SiC crystalline regions are formed by implanting carbon into regions of Si substrate and then annealing the substrate. An implant-stop layer is used to cover the Si device regions during formation of the SiC crystalline regions.
摘要翻译： 在上述Si衬底上形成SiC结晶区的机理能够在同一衬底上形成GaN和GaN基器件的集成。 通过将碳注入到Si衬底的区域中，然后使衬底退火来形成SiC晶体区域。 在形成SiC晶体区域期间，使用注入停止层来覆盖Si器件区域。
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公开(公告)号：US09111905B2
公开(公告)日：2015-08-18
申请号：US13434431
申请日：2012-03-29
申请人： Fu-Wei Yao , Chen-Ju Yu , King-Yuen Wong , Chun-Wei Hsu , Jiun-Lei Jerry Yu , Fu-Chih Yang , Chun Lin Tsai
发明人： Fu-Wei Yao , Chen-Ju Yu , King-Yuen Wong , Chun-Wei Hsu , Jiun-Lei Jerry Yu , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/66 , H01L29/417 , H01L29/778 , H01L29/08
CPC分类号： H01L29/452 , H01L21/0254 , H01L21/02543 , H01L21/02546 , H01L21/28575 , H01L29/0843 , H01L29/20 , H01L29/2003 , H01L29/205 , H01L29/41725 , H01L29/66462 , H01L29/7786 , H01L29/7787
摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A salicide source feature and a salicide drain feature are in contact with the first III-V compound layer through the second III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the salicide source feature and the salicide drain feature.
摘要翻译： 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 自杀剂源特征和自杀物排放特征通过第二III-V化合物层与第一III-V化合物层接触。 栅极电极设置在第一III-V化合物层的一部分之间，位于自对准硅化物源特征和自对准硅化物漏极特征之间。
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公开(公告)号：US09379191B2
公开(公告)日：2016-06-28
申请号：US13338962
申请日：2011-12-28
申请人： Chun-Wei Hsu , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chen-Ju Yu , Fu-Chih Yang , Chun Lin Tsai
发明人： Chun-Wei Hsu , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chen-Ju Yu , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/267 , H01L29/43 , H01L29/66 , H01L29/778 , H01L29/417 , H01L29/10 , H01L29/20
CPC分类号： H01L29/66462 , H01L21/02271 , H01L29/1066 , H01L29/2003 , H01L29/267 , H01L29/41766 , H01L29/432 , H01L29/7786 , H01L2924/0002
摘要： A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. The gate electrode includes a refractory metal. A depletion region is disposed in the carrier channel and under the gate electrode.
摘要翻译： 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 载体通道位于第一III-V化合物层和第二III-V化合物层之间。 源特征和漏极特征设置在第二III-V复合层上。 p型层设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。 栅电极设置在p型层上。 栅电极包括难熔金属。 耗尽区域设置在载流子通道中和栅电极下方。
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公开(公告)号：US08697505B2
公开(公告)日：2014-04-15
申请号：US13233356
申请日：2011-09-15
申请人： Po-Chih Chen , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Fu-Chih Yang , Chun Lin Tsai
发明人： Po-Chih Chen , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L21/338
CPC分类号： H01L29/7784 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/778 , H01L29/7787
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
摘要翻译： 公开了半导体结构。 半导体结构包括第一层。 第二层设置在第一层上并且与组合物中的第一层不同。 界面在第一层和第二层之间。 第三层设置在第二层上。 门设置在第三层上。 源极特征和漏极特征设置在栅极的相对侧上。 源特征和漏极特征中的每一个包括至少部分地嵌入第二和第三层中的对应金属特征。 相应的金属间化合物是每个金属特征的基础。 每个金属间化合物接触位于界面处的载体通道。
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公开(公告)号：US08507920B2
公开(公告)日：2013-08-13
申请号：US13180268
申请日：2011-07-11
申请人： Po-Chih Chen , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Fu-Chih Yang , Chun Lin Tsai
发明人： Po-Chih Chen , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/778
CPC分类号： H01L27/11578 , H01L21/28575 , H01L27/11565 , H01L29/0891 , H01L29/2003 , H01L29/42316 , H01L29/42376 , H01L29/452 , H01L29/66462 , H01L29/7787
摘要： An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
摘要翻译： 本公开的实施例包括半导体结构。 半导体结构包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 在第一III-V化合物层和第二III-V化合物层之间界定界面。 栅极设置在第二III-V复合层上。 源极特征和漏极特征设置在栅极的相对侧上。 源特征和漏极特征中的每一个包括至少部分地嵌入第二III-V化合物层中的对应金属特征。 相应的金属间化合物是每个金属特征的基础。 每个金属间化合物接触位于界面处的载体通道。
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公开(公告)号：US20130069116A1
公开(公告)日：2013-03-21
申请号：US13233356
申请日：2011-09-15
申请人： Po-Chih Chen , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Fu-Chih Yang , Chun Lin Tsai
发明人： Po-Chih Chen , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Fu-Chih Yang , Chun Lin Tsai
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7784 , H01L29/2003 , H01L29/205 , H01L29/66462 , H01L29/778 , H01L29/7787
摘要： A semiconductor structure is disclosed. The semiconductor structure includes a first layer. A second layer is disposed on the first layer and different from the first layer in composition. An interface is between the first layer and the second layer. A third layer is disposed on the second layer. A gate is disposed on the third layer. A source feature and a drain feature are disposed on opposite sides of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second and the third layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
摘要翻译： 公开了半导体结构。 半导体结构包括第一层。 第二层设置在第一层上并且与组合物中的第一层不同。 界面在第一层和第二层之间。 第三层设置在第二层上。 门设置在第三层上。 源极特征和漏极特征设置在栅极的相对侧上。 源特征和漏极特征中的每一个包括至少部分地嵌入第二和第三层中的对应金属特征。 相应的金属间化合物是每个金属特征的基础。 每个金属间化合物接触位于界面处的载体通道。
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公开(公告)号：US09099556B2
公开(公告)日：2015-08-04
申请号：US13213409
申请日：2011-08-19
申请人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
发明人： Chen-Liang Chu , Fei-Yuh Chen , Yi-Sheng Chen , Shih-Kuang Hsiao , Chun Lin Tsai , Kong-Beng Thei
CPC分类号： H01L29/41775 , H01L29/0653 , H01L29/0692 , H01L29/1033 , H01L29/1045 , H01L29/78 , H01L29/7823 , H01L29/7835
摘要： A semiconductor device includes an active region having a channel region and at least a wing region adjoining the channel region under the gate dielectric layer. The at least one wing region may be two symmetrical wing regions across the channel region.
摘要翻译： 半导体器件包括具有通道区域的有源区域和与栅极介电层下方的沟道区域邻接的至少一个翼区域。 所述至少一个机翼区域可以是穿过所述通道区域的两个对称翼区域。
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公开(公告)号：US20110163376A1
公开(公告)日：2011-07-07
申请号：US12652294
申请日：2010-01-05
申请人： Chih-Chang CHENG , Ruey-Hsin Liu , Chih-Wen Yao , Chia-Chin Shen , Eric Huang , Fu Chin Yang , Chun Lin Tsai , Hsiao-Chin Tuan
发明人： Chih-Chang CHENG , Ruey-Hsin Liu , Chih-Wen Yao , Chia-Chin Shen , Eric Huang , Fu Chin Yang , Chun Lin Tsai , Hsiao-Chin Tuan
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L27/088 , H01L24/16 , H01L24/48 , H01L29/063 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01068 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.
摘要翻译： 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。
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公开(公告)号：US08704312B2
公开(公告)日：2014-04-22
申请号：US12652294
申请日：2010-01-05
申请人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Chia-Chin Shen , Eric Huang , Fu Chin Yang , Chun Lin Tsai , Hsiao-Chin Tuan
发明人： Chih-Chang Cheng , Ruey-Hsin Liu , Chih-Wen Yao , Chia-Chin Shen , Eric Huang , Fu Chin Yang , Chun Lin Tsai , Hsiao-Chin Tuan
IPC分类号： H01L27/088
CPC分类号： H01L27/088 , H01L24/16 , H01L24/48 , H01L29/063 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/42368 , H01L29/456 , H01L29/495 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7816 , H01L2224/16225 , H01L2224/16227 , H01L2224/451 , H01L2224/48227 , H01L2924/00014 , H01L2924/01019 , H01L2924/01068 , H01L2924/13091 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A high voltage (HV) device includes a well region of a first dopant type disposed in a substrate. A first well region of a second dopant type is disposed in the well region of the first dopant type. An isolation structure is at least partially disposed in the well region of the first dopant type. A first gate electrode is disposed over the isolation structure and the first well region of the second dopant type. A second well region of the second dopant type is disposed in the well region of the first dopant type. The second well region of the second dopant type is spaced from the first well region of the second dopant type. A second gate electrode is disposed between and over the first well region of the second dopant type and the second well region of the second dopant type.
摘要翻译： 高压（HV）器件包括设置在衬底中的第一掺杂剂类型的阱区。 第二掺杂剂类型的第一阱区域设置在第一掺杂剂类型的阱区域中。 隔离结构至少部分地设置在第一掺杂剂类型的阱区中。 第一栅电极设置在隔离结构和第二掺杂剂类型的第一阱区之上。 第二掺杂剂类型的第二阱区设置在第一掺杂剂类型的阱区中。 第二掺杂剂类型的第二阱区域与第二掺杂剂类型的第一阱区域间隔开。 第二栅电极设置在第二掺杂剂类型的第一阱区域和第二掺杂剂类型的第二阱区域之间和之上。
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