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    Multi-socket network interface controller with consistent transaction ordering
    1.
    发明授权
    Multi-socket network interface controller with consistent transaction ordering 有权

    公开(公告)号：US12259832B2

    公开(公告)日：2025-03-25

    申请号：US18174668

    申请日：2023-02-27

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Tzahi Oved ,  Achiad Shochat ,  Liran Liss ,  Noam Bloch ,  Aviv Heller ,  Idan Burstein ,  Ariel Shahar ,  Peter Paneah

    IPC: G06F13/28 ,  G06F3/06

    Abstract: Computing apparatus includes a host computer, including multiple non-uniform memory access (NUMA) nodes, including at least first and second NUMA nodes, which include first and second local memories and first and second host bus interfaces for connection to first and second peripheral component buses, respectively. A network interface controller (NIC) is to receive a definition of a memory region extending over respective first and second parts of the first and second local memories and to receive a memory mapping with respect to the memory region that is applicable to both the first and second local memories, and to apply the memory mapping in writing data to the memory region via first and second NIC bus interfaces in a sequence of direct memory access (DMA) transactions to the respective first and second parts of the first and second local memories in response to packets received through a network port.

    Memory Access Tracking Using a Peripheral Device
    7.
    发明申请
    Memory Access Tracking Using a Peripheral Device 有权

    公开(公告)号：US20230133439A1

    公开(公告)日：2023-05-04

    申请号：US17536141

    申请日：2021-11-29

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Ran Avraham Koren ,  Ariel Shahar ,  Liran Liss ,  Gabi Liron ,  Aviad Shaul Yehezkel

    IPC: G06F12/0882 ,  G06F12/0831 ,  G06F13/16

    Abstract: A compute node includes a memory, a processor and a peripheral device. The memory is to store memory pages. The processor is to run software that accesses the memory, and to identify one or more first memory pages that are accessed by the software in the memory. The peripheral device is to directly access one or more second memory pages in the memory of the compute node using Direct Memory Access (DMA), and to notify the processor of the second memory pages that are accessed using DMA. The processor is further to maintain a data structure that tracks both (i) the first memory pages as identified by the processor and (ii) the second memory pages as notified by the peripheral device.

    Computational accelerator for packet payload operations
    8.
    发明申请
    Computational accelerator for packet payload operations 有权

    公开(公告)号：US20210203610A1

    公开(公告)日：2021-07-01

    申请号：US17204968

    申请日：2021-03-18

    Applicant: MELLANOX TECHNOLOGIES, LTD.

    Inventor： Boris Pismenny ,  Liran Liss ,  Ilya Lesokhin ,  Haggai Eran ,  Adi Menachem

    IPC: H04L12/833 ,  H04L29/06 ,  H04L12/931 ,  H04L29/08 ,  H04L12/851 ,  H04L12/413 ,  H04L12/00

    Abstract: Apparatus including a first interface to a host processor, a second interface to transmit and receive data packets having headers and payloads, to and from a packet communication network, a memory holding context information regarding a flow of the data and assigning serial numbers to the data packets in the flow, according to a session-layer protocol, and processing circuitry between the first and second interfaces and having acceleration logic, to decode the data records according to the session-layer protocol, using and updating the context information based on the serial numbers and the data records of the received packets, and processing circuitry writing the decoded data records through the first interface to a host memory. The acceleration logic, upon receiving in a given flow a data packet containing a serial number that is out of order, reconstructs the context information and applies that context information in decoding data records in subsequent data packets in the flow.

    Offloading communication security operations to a network interface controller
    9.
    发明授权
    Offloading communication security operations to a network interface controller 有权

    公开(公告)号：US10958627B2

    公开(公告)日：2021-03-23

    申请号：US16858874

    申请日：2020-04-27

    Applicant: Mellanox Technologies, Ltd.

    Inventor： Adi Menachem ,  Liran Liss ,  Boris Pismenny

    IPC: H04L29/06 ,  G06F21/60 ,  G06F21/53 ,  H04L9/08 ,  G06F9/455 ,  H04L9/14 ,  H04L9/32

    Abstract: Computing apparatus includes a host processor, which runs a virtual machine monitor (VMM), which supports a plurality of virtual machines and includes a cryptographic security software module. A network interface controller (NIC) links the host processor to a network so as to transmit and receive data packets from and to the virtual machines and includes a cryptographic security hardware logic module, which when invoked by the VMM, applies the cryptographic security protocol to the data packets while maintaining a state context of the protocol with respect to each of the virtual machines. Upon encountering an exception in applying the cryptographic security protocol, the NIC transfers the data packet, together with the state context of the cryptographic security protocol with respect to the given virtual machine, to the cryptographic security software module for processing.

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