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公开(公告)号：US20250054527A1
公开(公告)日：2025-02-13
申请号：US18806285
申请日：2024-08-15
Applicant: Micron Technology, Inc.
Inventor： Cheng Cheng Ang , Chun Lei Kong , Ting Luo , Aik Boon Edmund Yap
Abstract: Methods, systems, and devices for skipping pages for weak wordlines of a memory device during pre-programming are described. A memory device may be configured to operate in a first mode involving skipping one or more pages (e.g., a lower page (LP)) associated with a set of wordlines. In some examples, a testing system may determine the set of wordlines (e.g., weak wordlines) for which to skip pages according to performance degradation for the wordlines in response to applying a threshold temperature to a test memory device. In the first mode, the memory device may store (e.g., pre-program) data in a subset of pages distinct from the skipped pages. The memory device may switch to a second mode in response to a trigger condition. In the second mode, the memory device may use each page associated with the wordlines and may refrain from skipping the one or more pages.
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公开(公告)号：US20250036307A1
公开(公告)日：2025-01-30
申请号：US18912242
申请日：2024-10-10
Applicant: Micron Technology, Inc.
Inventor： Murong Lang , Christina Papagianni , Zhenming Zhou , Ting Luo
IPC: G06F3/06
Abstract: Methods, systems, and devices for cross-temperature mitigation in a memory system are described. A memory system may determine a first temperature of the memory system. Based on the first temperature satisfying a first threshold, the memory system may write a set of data to a first block of the memory system that is configured with a first rate for performing scan operations to determine error information for the first block. The memory system may then determine a second temperature of the memory system after writing the set of data to the first block. Based on the second temperature satisfying a second threshold, the memory system may transfer the set of data to a second block of the memory system that is configured with a second rate for performing scan operations to determine error information for the second block.
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公开(公告)号：US12079481B2
公开(公告)日：2024-09-03
申请号：US17898333
申请日：2022-08-29
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Chun Sum Yeung , Deping He , Ting Luo , Guang Hu , Jonathan S. Parry
IPC: G06F3/06
CPC classification number: G06F3/0611 , G06F3/0653 , G06F3/0679
Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.
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公开(公告)号：US20240021264A1
公开(公告)日：2024-01-18
申请号：US17812612
申请日：2022-07-14
Applicant: Micron Technology, Inc.
Inventor： Li-Te Chang , Murong Lang , Zhenming Zhou , Ting Luo
CPC classification number: G11C29/52 , G11C29/50004 , G11C29/783
Abstract: Methods, systems, and devices for read window management in a memory system are described. A memory system may determine, for a set of memory cells, a first value for a read window that is associated with a set of one or more threshold voltages each representing a different multi-bit value. The memory system may then use the first value for the read window to predict a second value for the read window. Based on the second value for the read window, the memory system may predict an error rate for the set of memory cells. The memory system may then set a value for an offset for a threshold voltage of the set of one or more threshold voltages based on the error rate.
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公开(公告)号：US20230274786A1
公开(公告)日：2023-08-31
申请号：US17681976
申请日：2022-02-28
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Sheyang Ning , Lawrence Celso Miranda , Tomoko Ogura Iwasaki , Ting Luo , Luyen Vu
CPC classification number: G11C29/42 , G11C29/4401 , G11C29/12005 , G11C7/1069 , G11C7/1096
Abstract: Apparatus might include an array of memory cells and a controller for access of the array of memory cells. The controller might be configured to cause the apparatus to apply a sense voltage level to a control gate of a memory cell of the array of memory cells, generate N determinations whether the memory cell is deemed to activate or deactivate while applying the sense voltage level, wherein N is an integer value greater than or equal to three, deem the memory cell to have a threshold voltage in a first range of threshold voltages lower than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell, and deem the memory cell to have a threshold voltage in a second range of threshold voltages higher than the sense voltage level in response to a majority of the N determinations indicating activation of the memory cell.
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Patent Agency Ranking
公开(公告)号：US11735269B2
公开(公告)日：2023-08-22
申请号：US17589172
申请日：2022-01-31
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Kulachet Tanpairoj , Harish Reddy Singidi , Jianmin Huang , Preston Allen Thomson , Sebastien Andre Jean
CPC classification number: G11C16/16 , G11C11/5635 , G11C16/0483 , G11C16/08 , G11C16/3445 , G11C11/5671 , G11C16/3409 , H10B41/27 , H10B43/27
Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.
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公开(公告)号：US11593032B1
公开(公告)日：2023-02-28
申请号：US17395695
申请日：2021-08-06
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Xiangang Luo , Jianmin Huang , Phong S. Nguyen
IPC: G06F3/06
Abstract: A method includes receiving a command to write data to a memory device and writing the data to a first memory tier of the memory device. The first memory tier of the memory device is a dynamic memory tier that utilizes single level cells (SLCs), multi-level cells (MLCs), and triple level cells (TLCs). The method further includes migrating the data from the first memory tier of the memory device to a second memory tier of the memory device. The second memory tier of the memory device is a static memory tier that utilizes quad level cells (QLCs).
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公开(公告)号：US11567682B2
公开(公告)日：2023-01-31
申请号：US16685300
申请日：2019-11-15
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Ankit Vinod Vashi , Xiangang Luo , Jianmin Huang
IPC: G06F3/06
Abstract: Techniques disclosed herein can be used to improve cross-temperature coverage of memory devices and improve memory device reliability in cross-temperature conditions. More specifically, a memory trim set can be selected from multiple candidate memory trim sets when performing a memory operation (such as a memory write operation), based on a temperature metric and a P/E cycle metric for the memory device. The candidate memory trim sets include multiple respective memory trim values (e.g., memory configuration parameters, such as program voltage step size, program pulse width, program verify level, etc., as discussed above) for performing the memory operation. The temperature metric can be indicative of a temperature of at least a region of the memory device (e.g., the entire device, a memory plane, a memory block, etc.), and the P/E cycle metric can be indicative of a number of P/E cycles performed by the memory device within a selected time interval.
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公开(公告)号：US20220375503A1
公开(公告)日：2022-11-24
申请号：US17882975
申请日：2022-08-08
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Tao Liu , Christopher J. Bueb , Eric Yuen , Cheng Cheng Ang
Abstract: A method includes monitoring a temperature of a memory component of a memory sub-system to determine that the temperature of the memory component corresponds to a first monitored temperature value; writing data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the first monitored temperature value; determining that the first monitored temperature value exceeds a threshold temperature range; monitoring the temperature of the memory component of the memory sub-system to determine that the temperature of the memory component corresponds to a second monitored temperature value that is within the threshold temperature range; and rewriting the data to the memory component of the memory sub-system while the temperature of the memory component corresponds to the second monitored temperature value.
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公开(公告)号：US11238939B2
公开(公告)日：2022-02-01
申请号：US17158555
申请日：2021-01-26
Applicant: Micron Technology, Inc.
Inventor： Ting Luo , Kulachet Tanpairoj , Harish Reddy Singidi , Jianmin Huang , Preston Allen Thomson , Sebastien Andre Jean
IPC: G11C11/34 , G11C16/16 , G11C16/04 , G11C16/08 , G11C11/56 , G11C16/34 , H01L27/11582 , H01L27/11556
Abstract: Disclosed in some examples are systems, methods, memory devices, and machine readable mediums for a fast secure data destruction for NAND memory devices that renders data in a memory cell unreadable. Instead of going through all the erase phases, the memory device may remove sensitive data by performing only the pre-programming phase of the erase process. Thus, the NAND doesn't perform the second and third phases of the erase process. This is much faster and results in data that cannot be reconstructed. In some examples, because the erase pulse is not actually applied and because this is simply a programming operation, data may be rendered unreadable at a per-page level rather than a per-block level as in traditional erases.
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