公开(公告)号：US06302732B1

公开(公告)日：2001-10-16

申请号：US09460888

申请日：1999-12-14

申请人： Mark Budman ,  Mario J. Interrante ,  John U. Knickerbocker

发明人： Mark Budman ,  Mario J. Interrante ,  John U. Knickerbocker

IPC分类号： H01R905

CPC分类号： H01R9/0515 ,  H01R13/03

摘要： A coaxial connector having a conductive copper wire core plated with a layer of gold with the layer of gold surrounded by a dielectric layer, such as polyimide. The layer of polyimide is surrounded by a conductive shielding layer, such as copper, with a tin-plated layer surrounding it. Connection of the coaxial connector at one end to adjacent signal and ground pads is achieved by laser ablation to expose a section of gold sufficient to accommodate the terminal pad pitch and allow wire bonding to the signal pad. Connection of the conductive shielding layer to the ground pad is achieved by hot tip soldering. Connection at the opposite end of the coaxial connector uses the same process.

摘要翻译： 一种同轴连接器，其具有镀有金层的导电铜线芯，该金属层由诸如聚酰亚胺之类的电介质层围绕的金属层。 聚酰亚胺层被诸如铜的导电屏蔽层包围，其周围具有镀锡层。 通过激光烧蚀来实现一端与相邻信号和接地焊盘的同轴连接器的连接，以暴露足以容纳端子焊盘间距并允许引线键合到信号焊盘的一部分金。 通过热尖端焊接实现导电屏蔽层与接地焊盘的连接。 同轴连接器相对端的连接使用相同的过程。

公开(公告)号：US06216937B1

公开(公告)日：2001-04-17

申请号：US09470455

申请日：1999-12-22

申请人： Stephen A. DeLaurentis ,  Mario J. Interrante ,  Raymond A. Jackson ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

发明人： Stephen A. DeLaurentis ,  Mario J. Interrante ,  Raymond A. Jackson ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC分类号： B23K100

CPC分类号： H01L21/687 ,  B23K1/018 ,  H01L24/98

摘要： A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bimetallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

摘要翻译： 一种用于通过在将模块加热到足以导致的温度的温度下向一个或多个倒装芯片的背面施加张力而将一个或多个去除构件施加拉力而移除通过安装在多芯片模块上的C4接头的倒装芯片的方法和装置 C4接头变得熔化。 张力可以是压缩弹簧，也可以是在室温下平坦并在加热到这样的温度时变得弯曲的双金属构件，或者原始形状是弯曲的并且在室温下弯曲平坦但回到其中的记忆合金 原来弯曲的形状加热到这样的温度。 使用粘合剂将去除构件粘合到要去除的芯片上，并且是固化后具有耐高温性的低温快速固化粘合剂。

公开(公告)号：US06360938B1

公开(公告)日：2002-03-26

申请号：US09794597

申请日：2001-02-27

申请人： Stephen A. DeLaurentis ,  Mario J. Interrante ,  Raymond A. Jackson ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

发明人： Stephen A. DeLaurentis ,  Mario J. Interrante ,  Raymond A. Jackson ,  John U. Knickerbocker ,  Sudipta K. Ray ,  Kathleen A. Stalter

IPC分类号： B23K1018

摘要： A process and apparatus for removing flip chips with C4 joints mounted on a multi-chip module by applying a tensile force to one or more removal member bonded to the back of one or more flip chips during heating of the module to a temperature sufficient to cause the C4 joints to become molten. The tensile force can either be a compressed spring, or a bi-metallic member which is flat at room temperature and becomes curved when heated to such temperature, or a memory alloy whose original shape is curved and which is bent flat at room temperature but returns to its original curved shape when heated to such temperature. An adhesive is used to bond the removal member to the chip to be removed and is a low temperature, fast curing adhesive with high temperature tolerance after curing.

公开(公告)号：US20130015440A1

公开(公告)日：2013-01-17

申请号：US13179868

申请日：2011-07-11

申请人： Bing Dang ,  John U. Knickerbocker ,  Yang Liu

发明人： Bing Dang ,  John U. Knickerbocker ,  Yang Liu

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/481 ,  G01R1/06761 ,  G01R1/07314 ,  G01R3/00 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A test probe head for probing integrated circuit (IC) chips and method of making test heads. The test head includes an array of vias (e.g., annular vias or grouped rectangular vias) through, and exiting one surface of, a semiconductor layer, e.g., a silicon layer. The vias, individual test probe tips, may be on a pitch at or less than fifty microns (50 μm). The probe tips may be stiffened with SiO2 (and optionally silicon) extending along the sidewalls. A redistribution layer connects individual test probe tips externally. The probe tips may be capped with a hardening cap that also caps stiffening SiO2 and silicon along the tip sidewall.

摘要翻译： 用于探测集成电路（IC）芯片的测试头和制造测试头的方法。 测试头包括穿过半导体层（例如硅层）并离开半导体层（例如硅层）的一个表面的通孔阵列（例如，环形通孔或分组的矩形通孔）。 通孔，单独的测试探针尖端可以在等于或小于50微米（50μm）的间距上。 探针尖端可以用沿着侧壁延伸的SiO 2（和任选的硅）加强。 再分配层外部连接各个测试探针。 探针尖端可以用硬化帽盖住，硬化帽也可以沿着尖端侧壁封闭加强SiO 2和硅。

公开(公告)号：US08227264B2

公开(公告)日：2012-07-24

申请号：US13071894

申请日：2011-03-25

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L21/30

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US07936060B2

公开(公告)日：2011-05-03

申请号：US12431827

申请日：2009-04-29

申请人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

发明人： Paul S. Andry ,  Stephen L. Buchwalter ,  George A. Katopis ,  John U. Knickerbocker ,  Stelios G. Tsapepas ,  Bucknell C. Webb

IPC分类号： H01L23/52

CPC分类号： H01L23/49827 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/00 ,  H01L2224/05552

摘要： An electronic device assembly is provided which includes a substrate, an interposer and an integrated circuit chip. The substrate is fabricated of a first material having a first thermal expansivity, and the interposer and integrated circuit chip are fabricated of a second material having a second thermal expansivity. The second thermal expansivity is different from the first thermal expansivity so that there is a coefficient of thermal expansion mismatch between the substrate and the interposer or chip. The interposer is coupled to the substrate via a first plurality of electrical contacts and an underfill adhesive at least partially surrounding the electrical contacts to bond the interposer to the substrate and thereby reduce strain on the first plurality of electrical contacts. The integrated circuit chip is coupled to the interposer via a second plurality of electrical contacts only, without use of an adhesive surrounding the second plurality of electrical contacts.

摘要翻译： 提供一种电子器件组件，其包括衬底，插入器和集成电路芯片。 衬底由具有第一热膨胀性的第一材料制成，并且插入器和集成电路芯片由具有第二热膨胀性的第二材料制成。 第二热膨胀性与第一热膨胀性不同，因此在衬底和插入件或芯片之间存在热膨胀失配系数。 插入器经由第一多个电触点和底部填充粘合剂耦合到基板，所述底部填充粘合剂至少部分地围绕电触点以将插入件结合到基板，从而减少第一多个电触点上的应变。 集成电路芯片仅通过第二多个电触点而耦合到插入器，而不使用围绕第二多个电触点的粘合剂。

公开(公告)号：US07836353B2

公开(公告)日：2010-11-16

申请号：US11745172

申请日：2007-05-07

申请人： John U. Knickerbocker ,  Gerard McVicker ,  Sri M. Sri-Jayantha

发明人： John U. Knickerbocker ,  Gerard McVicker ,  Sri M. Sri-Jayantha

IPC分类号： G06F11/00

CPC分类号： G06F1/206

摘要： A system for reducing an impact of hot spot pulsing of a semiconductor device including: first generating means for generating a plurality of local op-codes; a sequencer for augmenting customer op-codes with the plurality of local op-codes; selecting means for selecting one or more of the randomly arriving customer op-codes awaiting execution; monitoring means for tracking which of the one or more randomly arriving customer op-codes have been selected; separating means for separating the plurality of local op-codes from the one or more customer op-codes; storing means for storing one or more data related to the processing of the plurality of local op-codes and the customer op-codes; and second generating means for generating an output for a customer corresponding to that customer op-code while gainfully employing an output generated by local op-codes for system health monitoring purpose.

摘要翻译： 一种用于减少半导体器件的热点脉冲的影响的系统，包括：第一产生装置，用于产生多个本地操作码; 用于使用所述多个本地操作码增强客户操作码的定序器; 选择装置，用于选择等待执行的随机到达的客户操作码中的一个或多个; 用于跟踪所选择的一个或多个随机到达的客户操作代码中的哪一个的监视装置; 分离装置，用于从所述一个或多个客户操作码中分离所述多个本地操作码; 存储装置，用于存储与多个本地操作码和客户操作码的处理相关的一个或多个数据; 以及第二生成装置，用于在增益地采用由本地操作码产生的输出用于系统健康监视目的的同时，生成与该客户操作码对应的客户的输出。

公开(公告)号：US07791168B2

公开(公告)日：2010-09-07

申请号：US11930698

申请日：2007-10-31

申请人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L29/00 ,  H01L23/52 ,  H01L23/04 ,  H01L23/053

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device includes at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device including at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein includes the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其中包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。

公开(公告)号：US07784673B2

公开(公告)日：2010-08-31

申请号：US12189388

申请日：2008-08-11

申请人： Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

发明人： Steven A. Cordes ,  Peter A. Gruber ,  John U. Knickerbocker ,  James L. Speidell

IPC分类号： B23K31/02 ,  B23K37/00

CPC分类号： B23K3/0638 ,  B23K35/02 ,  B23K2101/40 ,  H01L2224/11

摘要： A system and method for injection molding conductive bonding material into a plurality of cavities in a non-rectangular mold is disclosed. The method comprises aligning a fill head with a non-rectangular mold. The non-rectangular mold includes a plurality of cavities. The fill head is placed in substantial contact with the non-rectangular mold. Rotational motion is provided to at least one of the non-rectangular mold and the fill head while the fill head is in substantial contact with the non-rectangular mold. Conductive bonding material is forced out of the fill head toward the non-rectangular mold. The conductive bonding material is provided into at least one cavity of the plurality of cavities contemporaneous with the at least one cavity being in proximity to the fill head.

摘要翻译： 公开了一种用于将导电接合材料注射成非矩形模具中的多个空腔的系统和方法。 该方法包括将填充头与非矩形模具对准。 非矩形模具包括多个空腔。 填充头被放置成与非矩形模具基本接触。 旋转运动提供给非矩形模具和填充头中的至少一个，同时填充头基本上与非矩形模具接触。 将导电接合材料从填充头推向非矩形模具。 导电接合材料被提供到与填充头附近的至少一个空腔同时的多个空腔的至少一个空腔中。

公开(公告)号：US07691669B2

公开(公告)日：2010-04-06

申请号：US12056852

申请日：2008-03-27

申请人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

发明人： Raymond R. Horton ,  John U. Knickerbocker ,  Edmund J. Sprogis ,  Cornelia K. Tsang

IPC分类号： H01L21/50 ,  H01L21/48 ,  H01L21/44 ,  H01L21/8242

CPC分类号： H01L23/49827 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/5382 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/01012 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/15311

摘要： Techniques for electronic device fabrication are provided. In one aspect, an electronic device is provided. The electronic device comprises at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein, the at least one interposer structure being configured to allow for one or more of the plurality of decoupling capacitors to be selectively deactivated. In another aspect, a method of fabricating an electronic device comprising at least one interposer structure having one or more vias and a plurality of decoupling capacitors integrated therein comprises the following step. One or more of the plurality of decoupling capacitors are selectively deactivated.

摘要翻译： 提供电子器件制造技术。 一方面，提供一种电子设备。 电子设备包括具有一个或多个通孔和集成在其中的多个去耦电容器的至少一个插入器结构，所述至少一个插入器结构被配置为允许选择性地去激活多个去耦电容器中的一个或多个。 在另一方面，一种制造电子器件的方法，包括至少一个具有一个或多个通孔的内插器结构和集成在其中的多个去耦电容器，其包括以下步骤。 选择性地去激活多个去耦电容器中的一个或多个。