Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号:US4748487A

    公开(公告)日:1988-05-31

    申请号:US053479

    申请日:1987-05-26

    CPC分类号: G11C11/419 H01L27/11

    摘要: A semiconductor memory device wherein the equivalent series resistances that are interposed in series in the pairs of complementary data lines D, D, are substantially the same as one another among the individual complementary data lines D, D. The equivalent series resistance is comprised of pull-up MISFET's and column switching MISFET's that exist between the power source V.sub.CC and the sense circuit. Parity is maintained for the pull-up MISFET's (Q.sub.p, Q.sub.p) and the column switching MISFET's (Q.sub.y, Q.sub.y) that exist on the pairs of complementary data lines D, D. To maintain this parity, the two MISFET's are formed to have the same shape. In addition, the arrangement of contacts to the transistors are set so that the directions in which the currents flow and lengths of current paths are also the same. In other words, contact portions between aluminum electrode and source and drain regions are formed at the same positions in the two MISFET's.

    摘要翻译: 一种半导体存储器件,其中在互补数据线对D,& D和D中的串联插入的等效串联电阻在各个互补数据线D,& L和D之间彼此基本相同。等效串联电阻包括 上拉MISFET和列切换MISFET存在于电源VCC和感测电路之间。 维持上拉MISFET(Qp,Qp)和在互补数据线D和上拉和下降D上存在的列切换MISFET(Qy,Qy)的奇偶校验。为了保持这个奇偶校验,两个MISFET的形成是 相同的形状。 此外,设置与晶体管的接触的布置,使得电流流动的方向和电流路径的长度也相同。 换句话说,铝电极和源极和漏极区域之间的接触部分形成在两个MISFET的相同位置处。