公开(公告)号：US12197264B2

公开(公告)日：2025-01-14

申请号：US17094579

申请日：2020-11-10

Applicant: Micron Technology, Inc.

Inventor： James S. Rehmeyer ,  Gary L. Howe ,  Miles S. Wiscombe ,  Eric J. Stave

IPC: G06F1/32 ,  G06F1/3203 ,  G11C11/40 ,  G11C11/4074

Abstract: Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.

公开(公告)号：US20240314990A1

公开(公告)日：2024-09-19

申请号：US18523591

申请日：2023-11-29

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: H05K9/00 ,  G11C11/408

CPC classification number: H05K9/0071 ,  G11C11/4087

Abstract: This disclosure is directed to circuitry for inducing jitter to clock signal of an electronic device to reduce undesired electromagnetic emissions of the electronic device during operation. The electronic device may include a jitter generator to induce the jitter to the clock signal. In some embodiments, the electronic device may also include a multiplexer outputting either of the clock signal or the jittered clock signal for latching the output signals. As such, the output signals may have a baseline margin based on the clock signal while the electronic device may operate using the jittered clock signal. The jittered clock signal may spread the undesired electromagnetic emissions of the electronic device and therefore reduce interference.

公开(公告)号：US20230117882A1

公开(公告)日：2023-04-20

申请号：US17494701

申请日：2021-10-05

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F3/06

Abstract: Methods, systems, and devices for on-die termination configuration for a memory device are described. In some examples, a memory device may determine a connection option from a set of connections options for which an ODT pin of the memory device is configured. Each connection option may correspond to a termination configuration for a different pin, such as a command and address (CA) pin, a clock (CK) pin, or a chip select (CS). Based on the determined connection option, the memory device may identify a respective termination option for each of the different pins, such as a first termination option for the CA pin, a second termination option for the CK pin, and a third termination option for the CS pin, and configure each of the different pins according to the respective termination option for that pin.

公开(公告)号：US20230021201A1

公开(公告)日：2023-01-19

申请号：US17939908

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Gary L. Howe ,  Miles S. Wiscombe ,  James S. Rehmeyer ,  Eric J. Stave

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/4074 ,  G11C5/14

Abstract: Methods, apparatuses, and systems related to voltage management of memory apparatuses/systems are described. The memory device can include circuitry configured to determine an operating frequency of a clock signal for an ongoing or an upcoming memory operation. The memory device may generate a control indicator for increasing a system voltage for higher operating frequencies, for decreasing the system voltage for lower operating frequencies, or a combination thereof.

公开(公告)号：US20220335000A1

公开(公告)日：2022-10-20

申请号：US17850927

申请日：2022-06-27

Applicant: Micron Technology, Inc.

Inventor： Thomas H. Kinsley ,  George E. Pax ,  Timothy M. Hollis ,  Yogesh Sharma ,  Randon K. Richards ,  Chan H. Yoo ,  Gregory A. King ,  Eric J. Stave

IPC: G06F13/42 ,  G06F11/10 ,  G11C7/10

Abstract: An apparatus is provided, comprising a plurality of memory devices and a buffering device that permits memory devices with a variety of physical dimensions and memory formats to be used in an industry-standard memory module format. The buffering device includes memory interface circuitry and at least one first-in first-out (FIFO) or multiplexer circuit. The apparatus further comprises a parallel bus connecting the buffering device to the plurality of memory devices. The parallel bus includes a plurality of independent control lines, each coupling the memory interface circuitry to a corresponding subset of a plurality of first subsets of the plurality of memory devices. The parallel bus further includes a plurality of independent data channels, each coupling the at least one FIFO circuit or multiplexer circuit to a corresponding subset of a plurality of second subsets of the plurality of memory devices.

公开(公告)号：US20220172755A1

公开(公告)日：2022-06-02

申请号：US17108850

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G11C7/22 ,  G11C7/02

Abstract: Devices, systems, and methods for timing elements of memory read and write operations are disclosed. A device may include a first DQ pin, a second DQ pin, and an output circuit. The output circuit may be configured to provide: a first signal at the first DQ pin and a second signal at the second DQ pin, based on the timing pattern. In some embodiments, based on the timing pattern, the output circuit may be configure to delay the first signal relative to the second signal such that rising and falling edges of the first signal do not coincide with rising and falling edges of the second signal. In these or other embodiments, the device may further include a mode register, wherein a slew rate of the first signal is based at least in part on a value of the mode register. Associated systems and methods are also disclosed.

公开(公告)号：US20220157396A1

公开(公告)日：2022-05-19

申请号：US17099694

申请日：2020-11-16

Applicant: Micron Technology, Inc.

Inventor： Markus H. Geiger ,  Anthony D. Newton ,  Ron A. Hughes ,  Eric J. Stave

IPC: G11C29/02 ,  G01R31/317 ,  G01R31/30 ,  G01R31/28

Abstract: Apparatuses for characterizing system channels and associated methods and systems are disclosed. In one embodiment, a tester is coupled to an adaptor configured to plug into a CPU socket of a system platform (e.g., a motherboard). The motherboard includes a memory socket that is connected to the CPU socket through system channels. The adaptor may include a connector configured to physically and electrically engage with the CPU socket, an interface configured to receive test signals from the tester, and circuitry configured to internally route the test signals to the connector. The adaptor, if plugged into the CPU socket, can facilitate the tester to directly assess signal transfer characteristics of the system channels. Accordingly, the tester can determine optimum operating parameters for the memory device in view of the system channel characteristics.

公开(公告)号：US20220058145A1

公开(公告)日：2022-02-24

申请号：US17387319

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave

IPC: G06F13/16 ,  G06F13/40 ,  G11C11/4076 ,  G11C11/4074 ,  G11C11/4072

Abstract: Methods, systems, and devices for addressing scheme for a memory system are described. A memory system may include a plurality of memory devices that are coupled with various command address (CA) channels via respective pins. In some examples, different pins of each memory device may be coupled with different CA channels. When the memory system receives a command to enter a memory device into a per-device addressability (PDA) mode, certain CA channels may be driven. One or more memory devices may enter the PDA mode based on certain pins of the respective memory device being biased.

公开(公告)号：US20240420790A1

公开(公告)日：2024-12-19

申请号：US18635869

申请日：2024-04-15

Applicant: Micron Technology, Inc.

Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

IPC: G11C29/42 ,  G11C29/12

Abstract: Systems and methods include receiving data bits at an input pin of a semiconductor device from a host device. The received data is latched in latch circuitries of the semiconductor device that at least partially implements an equalizer to aid in interpreting the received data bits. A first latched bit latched from the first received bit of the received bits is transmitted from the latch circuitries to self-calibration circuitry. The first received bit is also latched in error evaluation circuitry as a second latched bit. The second latched bit is transmitted from the error evaluation circuitry to the self-calibration circuitry. The self-calibration circuitry determines settings for the equalizer without involving the host device in determining the settings after the host device sends the data bits.

公开(公告)号：US20240249758A1

公开(公告)日：2024-07-25

申请号：US18623355

申请日：2024-04-01

Applicant: Micron Technology, Inc.

Inventor： Eric J. Stave ,  Dirgha Khatri ,  Elancheren Durai ,  Quincy R. Holton ,  Timothy M. Hollis ,  Matthew B. Leslie ,  Baekkyu Choi ,  Boe L. Holbrook ,  Yogesh Sharma ,  Scott R. Cyr

IPC: G11C8/18 ,  G11C7/10 ,  G11C8/06 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/1096 ,  G11C8/06 ,  G11C8/12

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).