公开(公告)号：US11676932B2

公开(公告)日：2023-06-13

申请号：US16806764

申请日：2020-03-02

Applicant: Micron Technology, Inc.

Inventor： Hyunsuk Chun ,  Thiagarajan Raman

IPC: H01L23/00

CPC classification number: H01L24/67 ,  H01L24/06 ,  H01L2924/3512

Abstract: Semiconductor devices having interconnect structures with narrowed portions configured to mitigate thermomechanical stresses, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a semiconductor die and a pillar structure coupled to the semiconductor die. The pillar structure can include an end portion away from the semiconductor die, the end portion having a first cross-sectional area. The pillar structure can further include a narrowed portion between the end portion and the semiconductor die, the narrowed portion having a second cross-sectional area less than the first-cross-sectional area of the end portion. A bond material can be coupled to the end portion of the pillar structure.

公开(公告)号：US11824025B2

公开(公告)日：2023-11-21

申请号：US17408343

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Thiagarajan Raman

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/433

CPC classification number: H01L24/06 ,  H01L21/56 ,  H01L23/296 ,  H01L23/4334 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05091 ,  H01L2224/06519 ,  H01L2924/35121

Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

公开(公告)号：US12300647B2

公开(公告)日：2025-05-13

申请号：US18380118

申请日：2023-10-13

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Thiagarajan Raman

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/29 ,  H01L23/433

Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

公开(公告)号：US20240055397A1

公开(公告)日：2024-02-15

申请号：US17884484

申请日：2022-08-09

Applicant: Micron Technology, Inc.

Inventor： Thiagarajan Raman ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L23/538 ,  H01L23/495 ,  H01L23/492 ,  H01L23/66 ,  H01L23/498

CPC classification number: H01L25/0655 ,  H01L23/5386 ,  H01L23/49575 ,  H01L23/492 ,  H01L23/66 ,  H01L23/49513 ,  H01L23/49805 ,  H01L25/18

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with through-substrate connections for recessed semiconductor dies. A semiconductor device assembly is described that includes a substrate having a first cavity and a second cavity. A first connective element is located at a side surface of the first cavity and a second connective element is located at a side surface of the second cavity. The semiconductor device assembly include a first semiconductor die and a second semiconductor die implemented at the first cavity and the second cavity, respectively. The first semiconductor die includes a third connective element at an edge surface of the die. The second semiconductor die includes a fourth connective element at an edge surface of the die. The dies are implemented at the cavities and connected through the connective elements to electrically couple the first die to the second die.

公开(公告)号：US20230056579A1

公开(公告)日：2023-02-23

申请号：US17408343

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Thiagarajan Raman

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L21/56

Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

公开(公告)号：US20240071914A1

公开(公告)日：2024-02-29

申请号：US17899586

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Thiagarajan Raman

IPC: H01L23/528 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/56 ,  H01L23/3178 ,  H01L23/5329 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48106

Abstract: A semiconductor device assembly is provided. The assembly includes a substrate with an inner and outer surface, a plurality of semiconductor devices disposed on the inner surface, a central interconnect structure disposed between the devices, a plurality of peripheral interconnect structures disposed around the devices, and an encapsulant material at least partially encapsulating the devices and the interconnects. The central interconnect structure includes a plurality of conductors and a sheath of dielectric material that surrounds and electrically isolates each of the plurality of conductors. Each of the peripheral interconnect structures is electrically coupled to at least one of the semiconductor devices. The encapsulant comprises a different material than the dielectric material.

公开(公告)号：US20240063156A1

公开(公告)日：2024-02-22

申请号：US18380118

申请日：2023-10-13

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Thiagarajan Raman

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/433 ,  H01L21/56

CPC classification number: H01L24/06 ,  H01L23/296 ,  H01L24/05 ,  H01L23/4334 ,  H01L21/56 ,  H01L24/03 ,  H01L2924/35121 ,  H01L2224/06519 ,  H01L2224/05091

Abstract: Semiconductor devices including electrically-isolated extensions and associated systems and methods are disclosed herein. An electrically-isolated extension may be coupled to a corresponding connection pad that is attached to a surface of a device. The electrically-isolated extensions may extend at least partially through one or more layers at or near the surface and toward a substrate or an inner portion thereof.

公开(公告)号：US20240047396A1

公开(公告)日：2024-02-08

申请号：US17882416

申请日：2022-08-05

Applicant: Micron Technology, Inc.

Inventor： Thiagarajan Raman

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L24/16 ,  H01L24/73 ,  H01L24/32 ,  H01L24/05 ,  H01L24/81 ,  H01L24/13 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06527 ,  H01L2225/06589 ,  H01L2224/81203 ,  H01L2224/8183 ,  H01L2224/81895 ,  H01L2224/80896 ,  H01L2224/05687 ,  H01L2224/13147 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/16145 ,  H01L2224/08145 ,  H01L2924/3511 ,  H01L2924/182 ,  H01L2224/16225 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/1431

Abstract: This document discloses techniques, apparatuses, and systems for a bonded semiconductor device. A semiconductor assembly is described that includes a first semiconductor die having a first surface and a second semiconductor die having a second surface. A first electrical contact coupled to the first semiconductor die protrudes from the first surface and couples, through a solder joint, to a second electrical contact that couples to the second semiconductor die and protrudes from the second surface. A first non-conductive bonding structure protrudes from the first surface and couples to a second non-conductive bonding structure that protrudes from the second surface.

公开(公告)号：US20240079369A1

公开(公告)日：2024-03-07

申请号：US17938917

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Terrence B. McDaniel ,  Bret K. Street ,  Wei Zhou ,  Kyle K. Kirby ,  Amy R. Griffin ,  Thiagarajan Raman ,  Jaekyu Song

IPC: H01L23/00 ,  H01L25/00

CPC classification number: H01L24/48 ,  H01L24/16 ,  H01L24/32 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48011 ,  H01L2224/4809 ,  H01L2224/48145 ,  H01L2224/4903 ,  H01L2224/49052 ,  H01L2224/73204 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1438

Abstract: This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.

公开(公告)号：US20240071891A1

公开(公告)日：2024-02-29

申请号：US17899577

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Thiagarajan Raman

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/182

Abstract: A semiconductor device assembly having face-to-face subassemblies is provided. The assembly includes a first and second semiconductor device subassembly. Both subassemblies include a substrate, a stack of semiconductor dies, and an interconnect structure. The interconnect structures include a conductive pillar surrounded by dielectric material. Both substrates form opposing outer sides of the assembly, while the interconnect structures are disposed on the inside surface of their respective substrates and are directly coupled to one another. The die stacks are shorter than their respective interconnect structures, and therefore can also be disposed on the inside surface of their respective substrates. An encapsulant material—comprising a different material than the dielectric material—at least partially encapsulates the stacks and the interconnect structures.