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15 条记录 (耗时 0.025 秒)

    Low-k dielectric layer with air gaps
    3.
    发明授权
    Low-k dielectric layer with air gaps 有权
    具有气隙的低k电介质层

    公开(公告)号：US06903002B1

    公开(公告)日：2005-06-07

    申请号：US10241236

    申请日：2002-09-11

    申请人： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Christopher A. Seams ,  Thurman J. Rodgers

    发明人： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Christopher A. Seams ,  Thurman J. Rodgers

    IPC分类号： H01L21/302 ,  H01L21/4763 ,  H01L21/768

    CPC分类号： H01L21/7682

    摘要： In one embodiment, a metal level includes a plurality of metal lines. A low-k dielectric is deposited over the metal level such that an air gap forms at least between two metal lines. The relatively low dielectric constant of the low-k dielectric reduces capacitance on metal lines regardless of whether an air gap forms or not. The air gap in the low-k dielectric further reduces capacitance on metal lines. The reduced capacitance translates to lower RC delay and faster signal propagation speeds.

    摘要翻译： 在一个实施例中，金属层包括多条金属线。 低k电介质沉积在金属层上，使得气隙至少形成在两条金属线之间。 低k介质的相对较低的介电常数降低金属线上的电容，而不管是否形成气隙。 低k电介质中的气隙进一步降低了金属线路上的电容。 减小的电容转换为较低的RC延迟和更快的信号传播速度。

    PROGRAMMABLE FLOATING GATE REFERENCE
    4.
    发明申请
    PROGRAMMABLE FLOATING GATE REFERENCE 有权
    可编程浮动栅参考

    公开(公告)号：US20080315847A1

    公开(公告)日：2008-12-25

    申请号：US12104678

    申请日：2008-04-17

    申请人： Harold Kutz ,  Warren Snyder ,  Thurman J. Rodgers

    发明人： Harold Kutz ,  Warren Snyder ,  Thurman J. Rodgers

    IPC分类号： G05F1/10

    CPC分类号： G11C5/145

    摘要： A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

    摘要翻译： 系统包括可产生电源电压的可控电压发生器。 该系统还包括一个系统控制器，用于确定与电源电压相关联的电压电平，并提示可控电压发生器产生电源电压。 该系统包括浮动栅极参考装置，用于至少部分地基于与电源电压相关联的电压电平来产生绝对电压基准。 该系统还可以包括模拟电路，以响应于来自浮动栅极参考装置的绝对电压基准来执行一个或多个电气操作。

    Wine-making press
    5.
    发明申请
    Wine-making press 审中-公开
    制酒新闻

    公开(公告)号：US20080102160A1

    公开(公告)日：2008-05-01

    申请号：US11588792

    申请日：2006-10-30

    申请人： Gregory Dixon Snell ,  Thomas Lorincz ,  Mike Ravkin ,  Thurman J. Rodgers ,  Richard Phipps

    发明人： Gregory Dixon Snell ,  Thomas Lorincz ,  Mike Ravkin ,  Thurman J. Rodgers ,  Richard Phipps

    IPC分类号： C12G1/00

    CPC分类号： C12G1/00 ,  C12G2200/31

    摘要： A wine-making pressing and fermenting apparatus that contains a compression-fermentation tank and a press plate moveable relative to the bottom of the tank due to engagement of a lead screw with a nut. According to one embodiment, the nut is fixed to the press tube that extends downward from the tank cover and engages the lead screw threaded into the nut from below and driven into rotation by the motor located under the tank in the tank supporting structure. According to another embodiment, the nut is fixed to the tank tube that extends upward from the tank bottom and engages the lead screw threaded into the nut from above and driven into rotation by the motor located over the tank and supported by the tank cover. The press plate has a plurality of through openings for squeezing out the grape juice.

    摘要翻译： 一种制酒压榨和发酵装置，其包含压缩发酵罐和压板，该压缩发酵罐和压板由于螺杆与螺母的接合而相对于罐的底部移动。 根据一个实施例，螺母固定到从罐盖向下延伸的压力管中，并从下方接合螺纹拧入螺母的导螺杆，并通过位于油箱支撑结构中的油箱下面的马达驱动旋转。 根据另一个实施例，螺母固定到从罐底向上延伸的罐管，并且从上方接合螺纹拧入螺母的导螺杆，并由位于罐上方的马达驱动旋转，并由油箱盖支撑。 压板具有多个用于挤出葡萄汁的通孔。

    VMOS Floating gate memory with breakdown voltage lowering region
    7.
    发明授权
    VMOS Floating gate memory with breakdown voltage lowering region 失效
    VMOS浮动栅极存储器，具有击穿电压降低区域

    公开(公告)号：US4222063A

    公开(公告)日：1980-09-09

    申请号：US910789

    申请日：1978-05-30

    申请人： Thurman J. Rodgers

    发明人： Thurman J. Rodgers

    IPC分类号： G11C16/04 ,  H01L29/788 ,  H01L27/10 ,  G11C11/40

    CPC分类号： H01L29/7886 ,  G11C16/0416 ,  Y10S257/927

    摘要： A semiconductor electrically programmable read only memory device (EPROM) utilizes an array of memory cells each in the form of a single V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and word line that extends across the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and word lines by thin oxide layers. A ring of P-type conductive material around the upper end of each V-shaped recess and adjacent its surrounding N-type drain region serves to lower the required programming voltage without increasing the device threshold voltage.

    摘要翻译： 半导体电可编程只读存储器件（EPROM）利用单个V型MOSFET形式的存储器单元阵列，其使用阈值逻辑的电容耦合版本来实现正常的与功能（数据字地址）。 每个MOSFET由位于每个位线和字线的交叉点处的V形凹槽形成，该位线延伸穿过扩散位线（其用作晶体管漏极）并进入衬底（其用作源极和接地平面 装置）。 类似的V形浮动栅极通过薄氧化物层隔离交叉位和字线的下方和上方。 围绕每个V形凹槽的上端并与其周围的N型漏极区相邻的P型导电材料环用于降低所需的编程电压而不增加器件阈值电压。

    Programmable floating gate reference
    8.
    发明授权
    Programmable floating gate reference 有权
    可编程浮动栅极参考

    公开(公告)号：US08106637B2

    公开(公告)日：2012-01-31

    申请号：US12104678

    申请日：2008-04-17

    申请人： Harold Kutz ,  Warren Snyder ,  Thurman J. Rodgers

    发明人： Harold Kutz ,  Warren Snyder ,  Thurman J. Rodgers

    IPC分类号： G05F1/46 ,  G05F3/16

    CPC分类号： G11C5/145

    摘要： A system includes a controllable voltage generator to generate a power supply voltage. The system also includes a system controller to determine a voltage level associated with the power supply voltage, and prompt the controllable voltage generator to generate the power supply voltage. The system includes a floating gate reference device to generate an absolute voltage reference based, at least in part, on the voltage level associated with the power supply voltage. The system can also include analog circuitry to perform one or more electrical operations responsive to the absolute voltage reference from the floating gate reference device.

    摘要翻译： 系统包括可产生电源电压的可控电压发生器。 该系统还包括一个系统控制器，用于确定与电源电压相关联的电压电平，并提示可控电压发生器产生电源电压。 该系统包括浮动栅极参考装置，用于至少部分地基于与电源电压相关联的电压电平来产生绝对电压基准。 系统还可以包括模拟电路，以响应于来自浮动栅极参考装置的绝对电压基准来执行一个或多个电气操作。

    Current source architecture for memory device standby current reduction
    9.
    发明授权
    Current source architecture for memory device standby current reduction 有权
    用于存储器件待机电流降低的电流源架构

    公开(公告)号：US07227804B1

    公开(公告)日：2007-06-05

    申请号：US10827785

    申请日：2004-04-19

    申请人： Badrinarayanan Kothandaraman ,  Eric Mann ,  Thurman J. Rodgers

    发明人： Badrinarayanan Kothandaraman ,  Eric Mann ,  Thurman J. Rodgers

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147 ,  G11C11/417

    摘要： A memory device (200) can include a memory cell block (202), a standby current source (206), an active current source (208), and a clamping device (212). In a standby mode, a standby current source (206) can provide constant standby current ISTBY to memory cell block (202) via block supply node (204). In an active mode, active current source (208) can provide current to accommodate current necessary for active operations (e.g., accessing the memory cell block). A clamping circuit (212) can provide additional current in the event a block supply node (204) potential VCCX collapses due to the presence of micro-defects. In addition, compensation for process variation can be achieved by a self regulating well (454) to source (404) back bias that can modulate the threshold voltage of p-channel transistors of memory cells within the well (454), reducing overall leakage.

    摘要翻译： 存储器件（200）可以包括存储器单元块（202），备用电流源（206），有源电流源（208）和钳位装置（212）。 在待机模式中，备用电流源（206）可以经由块供应节点（204）向存储器单元块（202）提供恒定待机电流I STBY。 在活动模式中，有源电流源（208）可以提供电流以适应有源操作（例如，访问存储器单元块）所需的电流。 在块供应节点（204）电位VCCX由于存在微缺陷而崩溃的情况下，钳位电路（212）可以提供额外的电流。 此外，可以通过自调节阱（454）到源（404）反向偏置来实现对过程变化的补偿，所述反向偏压可以调制阱（454）内的存储器单元的p沟道晶体管的阈值电压，从而减少总泄漏。

    VMOS Floating gate memory device
    10.
    发明授权
    VMOS Floating gate memory device 失效
    VMOS浮栅存储器件

    公开(公告)号：US4222062A

    公开(公告)日：1980-09-09

    申请号：US683185

    申请日：1976-05-04

    申请人： James D. Trotter ,  Thurman J. Rodgers

    发明人： James D. Trotter ,  Thurman J. Rodgers

    IPC分类号： H01L27/102 ,  G11C16/04 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8229 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/07 ,  H01L29/423 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10 ,  G11C11/40

    CPC分类号： H01L29/7886 ,  G11C16/0416 ,  G11C17/12 ,  H01L27/0733 ,  H01L27/10876 ,  H01L27/11553 ,  H01L29/7827 ,  H01L29/4236 ,  Y10S148/168 ,  Y10S257/927

    摘要： A semiconductor programmable read only memory device (PROM) utilizes an array of memory cells each having an area basically defined by the intersection of a bit line and a word address line. On a substrate of one conductivity type is an upper layer of material of the opposite conductivity within which are diffused bit lines of the same conductivity material as the substrate. The crossing address lines are conductive material formed on an insulating layer that covers the diffused bit lines and the upper layer. Each cell is a single transistor element in the form of a V-type MOSFET which achieves the normal AND function (Data-Word Address) using a capacitance coupled version of threshold logic. Each MOSFET is formed by a V-shaped recess at the intersection of each bit line and address line that extends through the diffused bit line, (which serves as the transistor drain) and into the substrate (which serves as the source and ground plane of the device). A similarly V-shaped floating gate is isolated below and above the crossing bit and address lines by thin oxide layers. Data is written into the cell when hot electrons are injected into the gate oxide near the drain junction and attracted to the floating gate which has been charged positive by capacitance coupling from the word line. The hot electrons are generated from the channel current via impact ionization at the pinched-off drain junction.

    摘要翻译： 半导体可编程只读存储器件（PROM）利用存储器单元阵列，每个存储器单元具有基本上由位线和字地址线的交点定义的区域。 在一种导电类型的衬底上是具有相反电导率的材料的上层，其中与衬底相同的导电材料的扩散位线。 交叉地址线是形成在覆盖扩散位线和上层的绝缘层上的导电材料。 每个单元是V型MOSFET形式的单晶体管元件，其使用阈值逻辑的电容耦合版本来实现正常的AND功能（数据字地址）。 每个MOSFET由位于每个位线和地址线的交叉处的V形凹槽形成，该位线延伸穿过扩散位线（其用作晶体管漏极）并进入衬底（其用作源极和接地平面 装置）。 类似的V形浮栅在交叉位和地址线的下方和上方被薄氧化物层隔离。 当热电子被注入到漏极结附近的栅极氧化物中时，数据被写入电池中，并被吸引到通过电容耦合从字线被正电荷的浮动栅极。 热电子通过在夹断漏极结处的冲击电离从沟道电流产生。