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    PACKAGE WITH A SUBSTRATE COMPRISING EMBEDDED STACKED TRENCH CAPACITOR DEVICES
    3.
    发明公开
    PACKAGE WITH A SUBSTRATE COMPRISING EMBEDDED STACKED TRENCH CAPACITOR DEVICES 审中-公开

    公开(公告)号：US20240038831A1

    公开(公告)日：2024-02-01

    申请号：US17878758

    申请日：2022-08-01

    Applicant: QUALCOMM Incorporated

    Inventor： Ryan LANE ,  Charles David PAYNTER ,  Durodami LISK ,  Darko POPOVIC ,  Yue LI ,  Shree Krishna PANDEY

    IPC: H01L49/02 ,  H01L23/522

    CPC classification number: H01L28/91 ,  H01L23/5223 ,  H01L24/16

    Abstract: A package comprising a substrate and an integrated device. The substrate includes a core layer comprising a first surface and a second surface; a plurality of core interconnects located in the core layer; at least one first dielectric layer coupled to the first surface of the core layer; a first plurality of interconnects located in the at least one first dielectric layer; at least one second dielectric layer coupled to the second surface of the core layer; a second plurality of interconnects located in the at least one second dielectric layer; and a capacitor structure located in the core layer. The capacitor structure includes a first trench capacitor device comprising a first front side and a first back side; and a second trench capacitor device coupled to the first trench capacitor device, where the second trench capacitor device comprises a second front side and a second back side.

    CUSTOM ORIENTATION OF SOCKET PINS TO ACHIEVE HIGH ISOLATION BETWEEN CHANNELS WITHOUT ADDING EXTRA REFERENCE PINS
    6.
    发明申请
    CUSTOM ORIENTATION OF SOCKET PINS TO ACHIEVE HIGH ISOLATION BETWEEN CHANNELS WITHOUT ADDING EXTRA REFERENCE PINS 审中-公开
    在不添加额外参考引脚的情况下，使用插针定位以实现通道之间的高隔离

    公开(公告)号：US20150372425A1

    公开(公告)日：2015-12-24

    申请号：US14313133

    申请日：2014-06-24

    Applicant: QUALCOMM Incorporated

    Inventor： Siamak FAZELPOUR ,  Charles David PAYNTER ,  Ryan David LANE

    IPC: H01R13/6461

    CPC classification number: H01R13/6461 ,  H01R12/714 ,  H01R43/205

    Abstract: Methods and apparatuses for reducing crosstalk. The method couples a first pin, having a first magnetic field direction, with a first socket. The method couples a second pin, having a second magnetic field direction, in a second socket. The method orients the first pin approximately orthogonally to the second pin such that the first magnetic field direction and the second magnetic field direction are approximately orthogonally oriented.

    Abstract translation: 减少串扰的方法和装置。 该方法将具有第一磁场方向的第一引脚与第一插座耦合。 该方法将具有第二磁场方向的第二销耦合到第二插座中。 所述方法将所述第一引脚大致正交于所述第二引脚，使得所述第一磁场方向和所述第二磁场方向近似正交定向。

    STACKED INTEGRATED CIRCUIT DEVICES
    7.
    发明申请
    STACKED INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20250062285A1

    公开(公告)日：2025-02-20

    申请号：US18451971

    申请日：2023-08-18

    Applicant: QUALCOMM Incorporated

    Inventor： Yue LI ,  Ryan LANE ,  Yangyang SUN ,  Charles David PAYNTER ,  Durodami LISK

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/16

    Abstract: A stacked integrated circuit (IC) device includes a first die having a first face, a first active region adjacent to the first face, and first die-interconnect contacts disposed on the first face and connected to first circuitry. The stacked IC device includes a second die having a second face, a second active region adjacent to the second face, and second die-interconnect contacts disposed on the second face and connected to second circuitry. The first face is oriented toward the second face, and the first die-interconnect contacts are connected to the second die-interconnect contacts. The stacked IC device includes a set of redistribution layers electrically connected to redistribution contacts on the first face, the second face, or both. The stacked IC device also includes interconnect conductors connected to the redistribution layers to provide signal paths from the first die, the second die, or both, to a set of external contacts.

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