公开(公告)号：US20190027427A1

公开(公告)日：2019-01-24

申请号：US16140791

申请日：2018-09-25

Applicant: RENESAS ELECTRONICS CORPORATION ,  RENESAS SEMICONDUCTOR PACKAGE & TEST SOLUTIONS CO., LTD.

Inventor： Hajime HASEBE ,  Tadatoshi DANNO ,  Yukihiro SATOU

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49 ,  H01L23/00

Abstract: In a non-leaded type semiconductor device, a tab, tab suspension leads, and other leads are exposed to one surface of a seal member. A semiconductor element is positioned within the seal member and fixed to a surface of the tab with an adhesive. The tab is formed larger than the semiconductor element so that outer peripheral edges of the tab are positioned outside outer peripheral edges of the semiconductor element. A groove is formed in the tab surface portion positioned between the area to which the semiconductor element is fixed and wire connection areas to which the wires are connected, the groove being formed so as to surround the semiconductor element fixing area, thereby preventing peeling-off between the tab to which the semiconductor element is fixed and the resin which constitutes the package.

公开(公告)号：US20150235987A1

公开(公告)日：2015-08-20

申请号：US14702969

申请日：2015-05-04

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Hiroyoshi TAYA ,  Yoshiharu SHIMIZU

IPC: H01L23/00 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/67144 ,  H01L21/6715 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/544 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/3701 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Abstract translation: 非铅半导体器件包括用于密封半导体芯片的密封体，密封体内部的凸片，用于支撑凸片的悬挂引线，具有暴露于密封体的后表面的外边缘部分的各个表面的引线 以及形成在半导体芯片和引线上的焊盘连接焊盘。 位于密封体的外周部的悬架引线的端部未被暴露在密封体的背面，而被密封体覆盖。 悬挂引线的分离部分不会在树脂模制中形成。 当切割悬挂引线时，密封体的后表面的角部由具有比悬挂引线的切割余量宽的区域的切割模具中的保持器部分的平坦部分支撑，从而防止了树脂的碎裂 。

公开(公告)号：US20180182692A1

公开(公告)日：2018-06-28

申请号：US15826815

申请日：2017-11-30

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA ,  Hiroyuki NAKAMURA

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/4952 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49575 ,  H01L23/49582 ,  H01L23/562 ,  H01L2224/05554 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/181 ,  H02P27/06 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. A SIP includes an analog chip, a microcomputer chip having a main surface smaller in area than a main surface of the analog chip, a die pad over which the analog chip and the microcomputer chip are mounted, and a plurality of leads arranged so as to surround the die pad. The SIP further includes a plurality of suspension leads formed integrally with the die pad, a plurality of wires electrically coupling electrodes of the analog chip to the leads and electrically coupling the microcomputer chip to the leads, and a sealing body sealing therein the analog chip and the microcomputer chip. Each of first and second curved portions of the die pad has a radius of curvature larger than a radius of curvature of a third curved portion of the die pad.

公开(公告)号：US20180151479A1

公开(公告)日：2018-05-31

申请号：US15715544

申请日：2017-09-26

Applicant: Renesas Electronics Corporation

Inventor： Atsushi NISHIKIZAWA ,  Tadatoshi DANNO

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

Abstract: In order to improve reliability of a semiconductor device, the semiconductor device includes a semiconductor chip, a die pad, a plurality of leads, and a sealing portion. The die pad and the leads are made of a metal material mainly containing copper. A plating layer is formed on a top surface of the die pad. The plating layer is formed by a silver plating layer, a gold plating layer, or a platinum plating layer. The semiconductor chip is mounted on the plating layer on the top surface of the die pad via a bonding material. The plating layer is covered by the bonding material not to be in contact with the sealing portion.

公开(公告)号：US20180047677A1

公开(公告)日：2018-02-15

申请号：US15729374

申请日：2017-10-10

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Hiroyoshi TAYA ,  Yoshiharu SHIMIZU

IPC: H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/544 ,  H01L21/78 ,  H01L21/67 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L24/83 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/67144 ,  H01L21/6715 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/544 ,  H01L23/562 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/3701 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

公开(公告)号：US20170301643A1

公开(公告)日：2017-10-19

申请号：US15641985

申请日：2017-07-05

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Atsushi NISHIKIZAWA

IPC: H01L23/00 ,  H01L23/047 ,  H01L23/367 ,  H01L23/495 ,  H01L23/498 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L24/73 ,  H01L21/4853 ,  H01L23/047 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49555 ,  H01L23/49575 ,  H01L23/49827 ,  H01L23/49844 ,  H01L24/05 ,  H01L24/06 ,  H01L24/09 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/4903 ,  H01L2224/49107 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/92247 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/15159 ,  H01L2924/181 ,  H05K1/0206 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An improvement is achieved in the reliability of a semiconductor device. Over a die pad, first and second semiconductor chips are mounted. The first and second semiconductor chips and a part of the die pad are sealed in a sealing portion. The first semiconductor chip includes a power transistor. The second semiconductor chip controls the first semiconductor chip. The thickness of the portion of the die pad over which the first semiconductor chip is mounted is smaller than the thickness of the portion of the die pad over which the second semiconductor chip is mounted.

公开(公告)号：US20170179010A1

公开(公告)日：2017-06-22

申请号：US15380183

申请日：2016-12-15

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Keita TAKADA ,  Tadatoshi DANNO

IPC: H01L23/495 ,  H01L23/00 ,  H04B5/00 ,  H01L23/498

CPC classification number: H01L23/49575 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49861 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05014 ,  H01L2224/05639 ,  H01L2224/29139 ,  H01L2224/29339 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48095 ,  H01L2224/48108 ,  H01L2224/48135 ,  H01L2224/48137 ,  H01L2224/48175 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49179 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/85439 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/181 ,  H04B5/0075 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Miniaturization of a semiconductor device is attained. An SOP1 includes: a semiconductor chip; another semiconductor chip; a die pad over which the former semiconductor chip is mounted; another die pad over which the latter semiconductor chip is mounted; a plurality of wires; and a sealing body. In plan view of the SOP1, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad. Also, in a horizontal direction in cross sectional view, the former semiconductor chip and the former die pad do not overlap the latter semiconductor chip and the latter die pad.

公开(公告)号：US20160351512A1

公开(公告)日：2016-12-01

申请号：US15236143

申请日：2016-08-12

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Hiroyoshi TAYA ,  Yoshiharu SHIMIZU

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/78 ,  H01L21/56 ,  H01L23/544 ,  H01L23/495 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L21/4825 ,  H01L21/4842 ,  H01L21/565 ,  H01L21/67144 ,  H01L21/6715 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/544 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32014 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/484 ,  H01L2224/48599 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/3512 ,  H01L2924/3701 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A non-leaded semiconductor device comprises a sealing body for sealing a semiconductor chip, a tab in the interior of the sealing body, suspension leads for supporting the tab, leads having respective surfaces exposed to outer edge portions of a back surface of the sealing body, and wires connecting pads formed on the semiconductor chip and the leads. End portions of the suspension leads positioned in an outer periphery portion of the sealing body are unexposed to the back surface of the sealing body, but are covered with the sealing body. Stand-off portions of the suspending leads are not formed in resin molding. When cutting the suspending leads, corner portions of the back surface of the sealing body are supported by a flat portion of a holder portion in a cutting die having an area wider than a cutting allowance of the suspending leads, whereby chipping of the resin is prevented.

Abstract translation: 非铅半导体器件包括用于密封半导体芯片的密封体，密封体内部的突片，用于支撑突片的悬挂引线，具有暴露于密封体的后表面的外边缘部分的各个表面的引线 以及形成在半导体芯片和引线上的焊盘连接焊盘。 位于密封体的外周部的悬架引线的端部未被暴露在密封体的背面，而被密封体覆盖。 悬挂引线的分离部分不会在树脂模制中形成。 当切割悬挂引线时，密封体的后表面的角部由具有比悬挂引线的切割余量宽的区域的切割模具中的保持器部分的平坦部分支撑，从而防止了树脂的碎裂 。

公开(公告)号：US20180076115A1

公开(公告)日：2018-03-15

申请号：US15818684

申请日：2017-11-20

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Tsukasa MATSUSHITA ,  Atsushi NISHIKIZAWA

IPC: H01L23/495 ,  H01L23/29 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/43 ,  H01L24/46 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/83

Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion. The distance between a lower side of the end surface of the first lead and an upper surface of the sealing portion is smaller than the distance between an upper side of the end surface of the second lead adjacent thereto and the upper surface of the sealing portion.

公开(公告)号：US20170309550A1

公开(公告)日：2017-10-26

申请号：US15462864

申请日：2017-03-19

Applicant: Renesas Electronics Corporation

Inventor： Tadatoshi DANNO ,  Tsukasa MATSUSHITA ,  Atsushi NISHIKIZAWA

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49541 ,  H01L21/4828 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/561 ,  H01L21/563 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3121 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/43 ,  H01L24/46 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2224/85 ,  H01L2224/83

Abstract: An improvement is achieved in the reliability of a semiconductor device. After a resin sealing portion is formed to seal a die pad, a semiconductor chip mounted over the die pad, a plurality of leads, and a plurality of wires electrically connecting a plurality of pad electrodes of the semiconductor chip with the leads, the resin sealing portion and the leads are cut with a rotary blade to manufacture the semiconductor device. In the semiconductor device, at least a portion of each of first and second leads is exposed from a lower surface of the sealing portion. End surfaces of the first and second leads as the respective cut surfaces thereof are exposed from each of side surfaces of the sealing portion as the cut surfaces of the resin sealing portion. The distance between a lower side of the end surface of the first lead and an upper surface of the sealing portion is smaller than the distance between an upper side of the end surface of the second lead adjacent thereto and the upper surface of the sealing portion.