公开(公告)号：US20250142874A1

公开(公告)日：2025-05-01

申请号：US18660936

申请日：2024-05-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Kyung-Eun BYUN ,  Minsu SEOL ,  Junyoung KWON ,  Huije RYU ,  Eunkyu LEE ,  Yeonchoo CHO

IPC: H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L29/66

Abstract: Provided is a semiconductor device including a substrate, a first vertical channel, a spacer, and a second vertical channel. The first vertical channel may have a sheet shape extending in a direction perpendicular to a surface of the substrate. The spacer may be provided at an end of the first vertical channel in an extension direction. The second vertical channel may be aligned with the first vertical channel on the spacer and have a sheet shape extending in a vertical direction.

公开(公告)号：US20250126846A1

公开(公告)日：2025-04-17

申请号：US18613829

申请日：2024-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung KWON ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Minsu SEOL

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device includes a first channel layer and a second channel layer spaced from each other in a first direction and each include a two-dimensional (2D) semiconductor material, a first source electrode between the first channel layer and the second channel layer to be simultaneously in contact with the first channel layer and the second channel layer, a first drain electrode between the first channel layer and the second channel layer to be spaced apart from the first source electrode in a second direction perpendicular to the first direction and simultaneously in contact with the first channel layer and the second channel layer, a first gate electrode arranged in a first internal space surrounded by the first source electrode, the first drain electrode, the first channel layer, and the second channel layer, and a first gate insulating layer surrounding the first gate electrode in the first internal space.

公开(公告)号：US20230157022A1

公开(公告)日：2023-05-18

申请号：US17986371

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Changhyun KIM ,  Sehun PARK ,  Hyunwoo KIM ,  Kyung-Eun BYUN ,  Dongjin YUN ,  Changseok LEE

IPC: H01L27/11582 ,  G06N3/063

CPC classification number: H01L27/11582 ,  G06N3/0635

Abstract: A vertical nonvolatile memory device may include a channel layer extending in a first direction; a plurality of gate electrodes and a plurality of spacers each extending in a second direction crossing the first direction, the plurality of gate electrodes and the plurality of spacers being alternately arranged with each other in the first direction; and a gate insulating layer extending in the first direction between the channel layer and the plurality of gate electrodes. Each of the plurality of gate electrodes may include a metal-doped graphene.

公开(公告)号：US20230081646A1

公开(公告)日：2023-03-16

申请号：US17902111

申请日：2022-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Unki KIM ,  Alum JUNG ,  Kyung-Eun BYUN

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L21/306 ,  H01L29/66

Abstract: A multi bridge channel field effect transistor includes a substrate, a first source/drain pattern on the substrate, a second source/drain pattern apart from the first source/drain pattern in a first direction on the substrate, a first channel layer and a second channel layer between the first source/drain pattern and the second source/drain pattern, a first graphene barrier between the first channel layer and the first source/drain pattern, a gate insulating layer surrounding the first channel layer, and a gate electrode surrounding the first channel layer with the gate insulating layer therebetween.

公开(公告)号：US20210206643A1

公开(公告)日：2021-07-08

申请号：US17138194

申请日：2020-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok LEE ,  Changhyun KIM ,  Kyung-Eun BYUN ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Eunkyu LEE

IPC: C01B32/186 ,  C01B32/194 ,  C23C16/02 ,  C23C16/04 ,  C23C16/26 ,  C23C16/513

Abstract: Provided is a method of selectively growing graphene. The method includes forming an ion implantation region and an ion non-implantation region by implanting ions locally into a substrate; and selectively growing graphene in the ion implantation region or the ion non-implantation region.

公开(公告)号：US20190205614A1

公开(公告)日：2019-07-04

申请号：US16163707

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Jae Mo SUNG ,  Youngwan SEO

IPC: G06K9/00 ,  G06T5/00 ,  G06T7/11 ,  H04N5/225

CPC classification number: G06K9/00201 ,  G06K9/00791 ,  G06T5/003 ,  G06T7/11 ,  G06T2207/20021 ,  G06T2207/30252 ,  H04N5/2256

Abstract: Disclosed is a method and apparatus for recognizing an object, the method including determining whether an image comprises a blur, determining a blur type of the blur based on control information of a vehicle, in response to the image comprising the blur, selecting a de-blurring scheme corresponding to the determined blur type, de-blurring the image using the selected de-blurring scheme, and recognizing an object in the image based the de-blurred image.

公开(公告)号：US20190161351A1

公开(公告)日：2019-05-30

申请号：US16183146

申请日：2018-11-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae SONG ,  Keunwook SHIN ,  Hyeonjin SHIN ,  Changseok LEE ,  Changhyun KIM ,  Kyungeun BYUN ,  Seungwon LEE ,  Eunkyu LEE

IPC: C01B32/186 ,  H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  C23C16/26 ,  C23C16/50

Abstract: Provided are nanocrystalline graphene and a method of forming the nanocrystalline graphene through a plasma enhanced chemical vapor deposition process. The nanocrystalline graphene may have a ratio of carbon having an sp2 bonding structure to total carbon within the range of about 50% to 99%. In addition, the nanocrystalline graphene may include crystals having a size of about 0.5 nm to about 100 nm.

公开(公告)号：US20180061490A1

公开(公告)日：2018-03-01

申请号：US15448998

申请日：2017-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Seunggeol NAM ,  Changhyun KIM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Jinseong HEO ,  Seongjun PARK

IPC: G11C13/00 ,  H01L45/00 ,  H01L27/24

CPC classification number: G11C13/0004 ,  G11C13/0069 ,  G11C13/0097 ,  H01L27/24 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1641

Abstract: A phase change memory device may include a phase change layer that includes a two-dimensional (2D) material. The phase change layer may include a layered structure that includes one or more layers of 2D material. The phase change layer may be provided between a first electrode and a second electrode, and the phase of at least a portion of one or more of the layers of 2D material may be changed based on an electrical signal applied to the phase change layer through the first electrode and the second electrode. The 2D material may include a chalcogenide-based material or phosphorene. The 2D material may be associated with a phase change temperature that is greater than or equal to about 200° C. and lower than or equal to about 500° C.

公开(公告)号：US20180047818A1

公开(公告)日：2018-02-15

申请号：US15439031

申请日：2017-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hyeonjin SHIN ,  Yeonchoo CHO ,  Minhyun LEE ,  Changhyun KIM ,  Seongjun PARK

IPC: H01L29/40 ,  H01L29/78

CPC classification number: H01L29/408 ,  H01L21/283 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/66568 ,  H01L29/78 ,  H01L29/7839 ,  H01L29/786

Abstract: A semiconductor device includes a silicon semiconductor layer including at least one region doped with a first conductive type dopant, a metal material layer electrically connected to the doped region, and a self-assembled monolayer (SAM) between the doped region and the metal material layer, the SAM forming a molecular dipole on an interface of the silicon semiconductor layer in a direction of reducing a Schottky barrier height (SBH).

公开(公告)号：US20250151438A1

公开(公告)日：2025-05-08

申请号：US18937958

申请日：2024-11-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongwoo HONG ,  Changhyun KIM ,  Byoungho LEE ,  Youngjin KIM ,  Gun-Yeal LEE ,  Junhyeok JANG ,  Yoonchan JEONG

IPC: H01L27/146 ,  G06F30/23

Abstract: A method of manufacturing a color-routing element, may include: generating an initial pattern; performing blurring on the initial pattern to generate a reference pattern; performing edge detection on the reference pattern to generate at least one comparison pattern reflecting a process error; performing a simulation to obtain at least one color-routing figure of merit based on the reference pattern and the at least one comparison pattern; updating the initial pattern based on a calculation result of the at least one color-routing figure of merit; generating the updated initial pattern as a target pattern of the color-routing element; and manufacturing the color-routing element based on the target pattern.