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    Three-dimensional semiconductor memory devices
    1.
    发明授权
    Three-dimensional semiconductor memory devices 有权
    三维半导体存储器件

    公开(公告)号：US08796091B2

    公开(公告)日：2014-08-05

    申请号：US14012588

    申请日：2013-08-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sung-Il Chang ,  Youngwoo Park ,  Kwang Soo Seol

    IPC: H01L21/336

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: Provided are three-dimensional semiconductor devices. A device includes an electrode structure including conductive patterns sequentially stacked on a substrate, a semiconductor pattern penetrating the electrode structure and including channel regions adjacent to the conductive patterns and vertical adjacent regions between the channel regions, and a semiconductor connecting layer extending from an outer sidewall of the semiconductor pattern to connect the semiconductor pattern to the substrate.

    Abstract translation: 提供三维半导体器件。 一种器件包括：电极结构，包括依次层叠在衬底上的导电图案，穿透电极结构的半导体图案，以及包括与导电图案相邻的沟道区域和沟道区域之间的垂直相邻区域;以及从外侧壁延伸的半导体连接层 的半导体图案以将半导体图案连接到基板。

    Memory device and method of storing data with error correction using codewords
    2.
    发明授权
    Memory device and method of storing data with error correction using codewords 有权
    使用码字进行纠错的存储装置和存储数据的方法

    公开(公告)号：US08543892B2

    公开(公告)日：2013-09-24

    申请号：US13625554

    申请日：2012-09-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwang Soo Seol ,  Sung-Il Park ,  Kyoung Lae Cho ,  In-Sung Joe

    IPC: G11C21/00

    CPC classification number: H03M13/611 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  H03M13/13 ,  H03M13/15 ,  H03M13/27 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/3715 ,  H03M13/47

    Abstract: Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.

    Abstract translation: 提供了存储器件和/或存储存储器数据位的方法。 存储器件包括包括多个MLC的多电平单元（MLC）阵列，纠错单元，被配置为编码要记录在MLC中的数据，其中编码数据被转换以将编码数据转换为码字， 错误模式分析单元，被配置为分析与包括在码字中的错误模式相对应的码字中包含的第一数据模式;以及数据转换单元，被配置为将分析的第一数据模式转换为第二数据模式。 根据上述存储器件和/或方法，可以有效地减少在数据存储较长时间段时发生的数据错误，从而提高可靠性。

    Memory Device And Method Of Storing Data With Error Correction Using Codewords
    3.
    发明申请
    Memory Device And Method Of Storing Data With Error Correction Using Codewords 有权
    使用代码字进行纠错存储数据的存储器件和方法

    公开(公告)号：US20130019143A1

    公开(公告)日：2013-01-17

    申请号：US13625554

    申请日：2012-09-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Kwang Soo Seol ,  Sung-Il Park ,  Kyoung Lae Cho ,  In-sung Joe

    IPC: H03M13/05

    CPC classification number: H03M13/611 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5642 ,  G11C16/26 ,  G11C29/00 ,  H03M13/13 ,  H03M13/15 ,  H03M13/27 ,  H03M13/2732 ,  H03M13/2906 ,  H03M13/3707 ,  H03M13/3715 ,  H03M13/47

    Abstract: Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability.

    Abstract translation: 提供了存储器件和/或存储存储器数据位的方法。 存储器件包括包括多个MLC的多电平单元（MLC）阵列，纠错单元，被配置为编码要记录在MLC中的数据，其中编码数据被转换以将编码数据转换为码字， 错误模式分析单元，被配置为分析与包括在码字中的错误模式相对应的码字中包含的第一数据模式;以及数据转换单元，被配置为将分析的第一数据模式转换为第二数据模式。 根据上述存储器件和/或方法，可以有效地减少在数据存储较长时间段时发生的数据错误，从而提高可靠性。

    Non-volatile memory devices having reduced susceptibility to leakage of stored charges
    7.
    发明授权
    Non-volatile memory devices having reduced susceptibility to leakage of stored charges 有权
    具有降低对存储的电荷泄漏的敏感性的非易失性存储器件

    公开(公告)号：US09082750B2

    公开(公告)日：2015-07-14

    申请号：US14218293

    申请日：2014-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Albert Fayrushin ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC: H01L29/788 ,  H01L29/76 ,  H01L29/423 ,  H01L27/115 ,  H01L29/66 ,  H01L29/792

    CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

    Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

    NON-VOLATILE MEMORY DEVICES HAVING REDUCED SUSCEPTIBILITY TO LEAKAGE OF STORED CHARGES AND METHODS OF FORMING SAME
    8.
    发明申请
    NON-VOLATILE MEMORY DEVICES HAVING REDUCED SUSCEPTIBILITY TO LEAKAGE OF STORED CHARGES AND METHODS OF FORMING SAME 审中-公开
    具有降低的储存容量泄漏的不挥发性记忆装置及其形成方法

    公开(公告)号：US20140197471A1

    公开(公告)日：2014-07-17

    申请号：US14218293

    申请日：2014-03-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Albert Fayrushin ,  Kwang Soo Seol ,  Jaeduk Lee

    IPC: H01L29/423 ,  H01L29/792 ,  H01L29/788

    CPC classification number: H01L29/4234 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: Provided is a semiconductor device. The semiconductor device includes a substrate, a tunnel insulating layer, a charge storage pattern, a blocking layer, a gate electrode. The tunnel insulating layer is disposed over the substrate. The charge storage pattern is disposed over the tunnel insulating layer. The charge storage pattern has an upper surface, a sidewall, and an edge portion between the upper surface and the sidewall. The blocking layer includes an insulating pattern covering the edge portion of the charge storage pattern, and a gate dielectric layer covering the upper surface, the sidewall, and the edge portion of the charge storage pattern. The gate electrode is disposed over the blocking layer, the gate electrode covering the upper surface, the sidewall, and the edge portion of the charge storage pattern.

    Abstract translation: 提供一种半导体器件。 半导体器件包括衬底，隧道绝缘层，电荷存储图案，阻挡层，栅电极。 隧道绝缘层设置在衬底上。 电荷存储图案设置在隧道绝缘层上。 电荷存储图案具有在上表面和侧壁之间的上表面，侧壁和边缘部分。 阻挡层包括覆盖电荷存储图案的边缘部分的绝缘图案，以及覆盖电荷存储图案的上表面，侧壁和边缘部分的栅极电介质层。 栅电极设置在阻挡层上，栅电极覆盖电荷存储图案的上表面，侧壁和边缘部分。

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