公开(公告)号：US11749592B2

公开(公告)日：2023-09-05

申请号：US17348936

申请日：2021-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk Kwon ,  Jiwon Shin ,  Kwangbok Woo ,  Minseung Ji

IPC: H01L23/498 ,  H01L23/32 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10

CPC classification number: H01L23/49833 ,  H01L23/3121 ,  H01L23/32 ,  H01L23/49816 ,  H01L24/16 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058

Abstract: A lower semiconductor package of a package-on-package type semiconductor package includes: a package substrate; a semiconductor chip mounted on the package substrate; a chip connecting terminal disposed between the semiconductor chip and the package substrate and configured to connect the semiconductor chip to the package substrate; conductive pillars arranged on the package substrate to at least partially surround the semiconductor chip; and a dam structure configured to cover the conductive pillars on the package substrate and having a first opening at least partially surrounding the semiconductor chip.

公开(公告)号：US12288745B2

公开(公告)日：2025-04-29

申请号：US17844815

申请日：2022-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Donguk Kwon ,  Wooram Myung ,  Jiwon Shin ,  Pilsung Choi

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/48 ,  H01L25/10

Abstract: A semiconductor package includes a lower substrate having a chip mounting region, an interconnection region surrounding the chip mounting region, and an outer region surrounding the interconnection region, and includes a lower wiring layer. A first solder resist pattern has first openings exposing bonding regions of the lower wiring layer. A semiconductor chip is on the chip mounting region and is electrically connected to the lower wiring layer. A second solder resist pattern is on the first solder resist pattern on the interconnection and outer regions and is spaced apart from the semiconductor chip, and includes second openings disposed on the first openings. An upper substrate covers the semiconductor chip, and includes an upper wiring layer. A vertical connection structure is on the interconnection region and electrically connects the upper and lower wiring layers. A solder resist spacer is on the second solder resist pattern on the outer region.

公开(公告)号：US11676904B2

公开(公告)日：2023-06-13

申请号：US17328297

申请日：2021-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Shin ,  Donguk Kwon ,  Kwang Bok Woo ,  Minseung Ji

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L23/367

CPC classification number: H01L23/5385 ,  H01L23/367 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/73204 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06506 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2924/15156 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

公开(公告)号：US12272652B2

公开(公告)日：2025-04-08

申请号：US18140985

申请日：2023-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Shin ,  Donguk Kwon ,  Kwang Bok Woo ,  Minseung Ji

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/367 ,  H01L25/065

Abstract: A semiconductor package includes a first sub-semiconductor device, an interposer, and a second sub-semiconductor device stacked on each other, and a heat sink covering the second sub-semiconductor device. The first sub-semiconductor device includes a first substrate and a first semiconductor chip. The interposer includes a dielectric layer, a thermal conductive layer in contact with a bottom surface of the dielectric layer, a first thermal conductive pad in contact with a top surface of the dielectric layer, and thermal conductive vias penetrating the dielectric layer to connect the thermal conductive layer to the first thermal conductive pad. A bottom surface of the thermal conductive layer is adjacent to and connected to a top surface of the first semiconductor chip. The second sub-semiconductor device is disposed on the dielectric layer without overlapping the first thermal conductive pad. The heat sink further covers the first thermal conductive pad to be connected thereto.

公开(公告)号：US20240321823A1

公开(公告)日：2024-09-26

申请号：US18531883

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Donguk Kwon ,  Gongmyeong Kim ,  Sunchul Kim ,  Chaein Moon ,  Hyeonrae Cho

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

CPC classification number: H01L24/83 ,  H01L21/481 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L25/18 ,  H10B80/00 ,  H01L24/48 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/1312 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13169 ,  H01L2224/16227 ,  H01L2224/32237 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81193 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/014 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/1443

Abstract: Provided is a semiconductor package with enhanced reliability and a method of manufacturing the same. The semiconductor package includes a package substrate including a body layer having a central area and a peripheral area, a first protective layer on a top surface of the body layer, and a second protective layer on the first protective layer in the peripheral area, a semiconductor chip mounted on the first protective layer in the central area in a flip-chip structure, an underfill in a gap between the first protective layer and the semiconductor chip and in a gap between the connection terminals, an interposer on the semiconductor chip, and inter-substrate connection terminals on the peripheral area of the package substrate and electrically connecting the package substrate to the interposer, where the underfill has an anchor structure extending into the first protective layer.

公开(公告)号：US20240170448A1

公开(公告)日：2024-05-23

申请号：US18470082

申请日：2023-09-19

Applicant: SAMSUNG ELECTRONICS CO.,LTD.

Inventor： Sanghyeon Jeong ,  Youngja Kim ,  Junga Lee ,  Donguk Kwon

IPC: H01L23/00

CPC classification number: H01L24/81 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/81801 ,  H01L2924/3511

Abstract: A method of manufacturing a semiconductor package includes applying a plurality of forces to a plurality of points of a semiconductor chip through a plurality of elastic members, and bonding the semiconductor chip to an object while the plurality of forces are applied to the plurality of points of the semiconductor chip through the plurality of elastic members, wherein the plurality of elastic members are configured such that the plurality of forces are different from each other, and the plurality of forces flatten the semiconductor chip.