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公开(公告)号：US11038495B1
公开(公告)日：2021-06-15
申请号：US16838847
申请日：2020-04-02
Applicant: Silicon Storage Technology, Inc.
Inventor： Ryan Mei , Xiaozhou Qian , Hieu Van Tran , Claire Zhu
IPC: H03K3/356 , H03K19/185 , H03K19/003 , H03K19/0185
Abstract: An improved level shifter is disclosed. The level shifter is able to achieve a switching time below 1 ns using a relatively low voltage for VDDL, such as 0.75 V. The improved level shifter comprises a coupling stage and a level-switching stage. A related method of level shifting is also disclosed.
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公开(公告)号：US10199109B2
公开(公告)日：2019-02-05
申请号：US15371496
申请日：2016-12-07
Applicant: Silicon Storage Technology, Inc.
Inventor： Xiaozhou Qian , Xiao Yan Pi , Kai Man Yue , Qing Rao , Lisa Bian
Abstract: Multiple embodiments of a low power sense amplifier for use in a flash memory system are disclosed. In some embodiments, the loading on a sense amplifier can be adjusted by selectively attaching one or more bit lines to the sense amplifier, where the one or more bit lines each is coupled to an extraneous memory cell.
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公开(公告)号：US09589630B2
公开(公告)日：2017-03-07
申请号：US14435251
申请日：2013-10-03
Applicant: Silicon Storage Technology, Inc.
Inventor： Yao Zhou , Xiaozhou Qian , Guangming Lin
CPC classification number: G11C11/5642 , G05F3/262 , G11C5/147 , G11C7/062 , G11C7/12 , G11C16/28 , G11C2207/063
Abstract: The invention comprises a non-volatile memory device with a sensing amplifier that includes a current mirror comprising a pair of resistors.
Abstract translation: 本发明包括具有感测放大器的非易失性存储器件，该感测放大器包括包括一对电阻器的电流镜。
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4.发明申请System And Method For Programming Split-Gate, Non-volatile Memory Cells 审中-公开用于编程分离门，非易失性存储单元的系统和方法公开(公告)号：US20160336072A1
公开(公告)日：2016-11-17
申请号：US15084955
申请日：2016-03-30
Applicant: Silicon Storage Technology, Inc.
Inventor： Xiaozhou Qian , Viktor Markov , Jong-Won Yoo , Xiao Yan Pi , Alexander Kotov
CPC classification number: G11C16/12 , G11C16/0425 , G11C16/10
Abstract: The disclosed embodiments comprise a flash memory device and a method of programming the device in a way that reduces degradation of the device compared to prior art methods.
Abstract translation: 所公开的实施例包括闪存器件和以与现有技术方法相比降低器件劣化的方式对器件进行编程的方法。
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公开(公告)号：US20150235711A1
公开(公告)日：2015-08-20
申请号：US14435251
申请日：2013-10-03
Applicant: SILICON STORAGE TECHNOLOGY INC.
Inventor： Yao Zhou , Xiaozhou Qian , Guangming Lin
IPC: G11C16/28
CPC classification number: G11C11/5642 , G05F3/262 , G11C5/147 , G11C7/062 , G11C7/12 , G11C16/28 , G11C2207/063
Abstract: A non-volatile memory device with a sensing amplifier (10) that includes a current mirror comprising a pair of resistors (20,30) and an operational amplifier (40) is disclosed.
Abstract translation: 公开了一种具有感测放大器（10）的非易失性存储器件，该感测放大器（10）包括包括一对电阻器（20,30）和运算放大器（40）的电流镜。
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Patent Agency Ranking
6.发明公开公开(公告)号：US20230170035A1
公开(公告)日：2023-06-01
申请号：US17669793
申请日：2022-02-11
Applicant: Silicon Storage Technology, Inc.
Inventor： Xiaozhou Qian , YAOHUA ZHU
Abstract: Various embodiments are disclosed for performing address fault detection in a memory system using a hierarchical ROM encoding system. In one embodiment, a hierarchical ROM encoding system comprises two levels of ROM encoders that are used to detect an address fault. In another embodiment, a hierarchical ROM encoding system comprises three levels of ROM encoders that are used to detect an address fault.
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公开(公告)号：US20210264996A1
公开(公告)日：2021-08-26
申请号：US17006550
申请日：2020-08-28
Applicant: Silicon Storage Technology, Inc.
Inventor： Guangming Lin , Xiaozhou Qian , Xiao Yan Pi , Vipin Tiwari , Zhenlin Ding
Abstract: The present invention relates to systems and methods for implementing wear leveling in a flash memory device that emulates an EEPROM. The embodiments utilize an index array, which stores an index word for each logical address in the emulated EEPROM. Each bit in each index word is associated with a physical address for a physical word in the emulated EEPROM, and the index word keeps track of which physical word is the current word for a particular logical address. The use of the index word enables a wear leveling algorithm that allows for a programming command to a logical address to result in: (i) skipping the programming operation if the data stored in the current word does not contain a “1” that corresponds to a “0” in the data to be stored, (ii) reprogramming one or more bits of the current word in certain situations, or (iii) shifting to and programming the next physical word in certain situations.
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8.发明授权公开(公告)号：US10181354B2
公开(公告)日：2019-01-15
申请号：US15690159
申请日：2017-08-29
Applicant: Silicon Storage Technology, Inc.
Abstract: The present invention relates to an improved sense amplifier for reading values in flash memory cells in an array. In one embodiment, a sense amplifier comprises an improved pre-charge circuit for pre-charging a bit line during a pre-charge period to increase the speed of read operations. In another embodiment, a sense amplifier comprises simplified address decoding circuitry to increase the speed of read operations.
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公开(公告)号：US09601500B2
公开(公告)日：2017-03-21
申请号：US14639063
申请日：2015-03-04
Applicant: Silicon Storage Technology, Inc.
Inventor： Jinho Kim , Vipin Tiwari , Nhan Do , Xian Liu , Xiaozhou Qian , Ning Bai , Kai Man Yue
IPC: H01L27/115 , H01L29/423 , H01L29/788
CPC classification number: H01L27/11524 , H01L23/57 , H01L27/11226 , H01L27/11233 , H01L27/11253 , H01L27/11519 , H01L29/42328 , H01L29/788 , H01L29/7881
Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.
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公开(公告)号：US20160379941A1
公开(公告)日：2016-12-29
申请号：US15258069
申请日：2016-09-07
Applicant: Silicon Storage Technology, Inc.
Inventor： Jinho Kim , Vipin Tiwari , Nhan Do , Xian Liu , Xiaozhou Qian , Ning Bai , Kai Man Yue
IPC: H01L23/00 , H01L29/423 , H01L27/115 , H01L29/788
CPC classification number: H01L27/11524 , H01L23/57 , H01L27/11226 , H01L27/11233 , H01L27/11253 , H01L27/11519 , H01L29/42328 , H01L29/788 , H01L29/7881
Abstract: A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.
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