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公开(公告)号：US10033518B2
公开(公告)日：2018-07-24
申请号：US15703792
申请日：2017-09-13
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tapas Nandy , Nitin Gupta
Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
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2.发明授权Output common mode voltage stabilizer over large common mode input range in a high speed differential amplifier 有权在高速差分放大器的大共模输入范围内输出共模稳压器公开(公告)号：US08502603B2
公开(公告)日：2013-08-06
申请号：US13735114
申请日：2013-01-07
Applicant: STMicroelectronics International N.V.
Inventor： Tapas Nandy , Surendra Kumar
IPC: H03F3/45
CPC classification number: H03F3/45071 , H03F1/0266 , H03F3/45192 , H03F3/45632 , H03F2200/453 , H03F2200/456 , H03F2203/45302 , H03F2203/45354 , H03F2203/45418 , H03F2203/45424 , H03F2203/45434 , H03F2203/45446 , H03F2203/45702
Abstract: A circuit includes a differential amplifier having a folded cascode architecture with a pair of cascode transistors. A sensing circuit senses a common mode input voltage of a differential input signal applied to the differential amplifier. A bias generator circuit generates a bias voltage for application to the pair of cascode transistors in the folded cascode architecture. The bias generator circuit is connected to an output of the sensing circuit such that the generated bias voltage has a value which is dependent on the sensed common mode input voltage. This dependence stabilizes a common mode output voltage from the differential amplifier in response to changes in the common mode input voltage.
Abstract translation: 电路包括具有折叠共源共栅结构的差分放大器和一对共源共栅晶体管。 感测电路感测施加到差分放大器的差分输入信号的共模输入电压。 偏置发生器电路在折叠共源共栅结构中产生用于施加到该对共源共栅晶体管的偏置电压。 偏置发生器电路连接到感测电路的输出，使得产生的偏置电压具有取决于感测到的共模输入电压的值。 这种依赖性响应于共模输入电压的变化而稳定来自差分放大器的共模输出电压。
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公开(公告)号：US20170276710A1
公开(公告)日：2017-09-28
申请号：US15618269
申请日：2017-06-09
Applicant: STMicroelectronics International N.V.
Inventor： Daljeet Kumar , Tapas Nandy , Surendra Kumar
CPC classification number: G01R19/04 , G01R19/2503
Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.
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4.发明授权Syncless unit interval variation tolerant PWM receiver circuit, system and method 有权同步单元间隔变化容限PWM接收电路，系统及方法公开(公告)号：US09425781B2
公开(公告)日：2016-08-23
申请号：US14231133
申请日：2014-03-31
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Tapas Nandy , Anchal Jain
IPC: H03K9/08
CPC classification number: H03K9/08
Abstract: A PWM receiver circuit receives and demodulates pulse width modulated (PWM) data signals without requiring synchronization such that no synchronization preamble need be provided with the PWM data signal. Embodiments may consume less power since there is no need to repeatedly synchronize a PLL, counter or other circuitry to the PWM data signal. Furthermore, the PWM receiver circuit operates in view of or is “tolerant” to jitter in the frequency of the PWM signal and also to a relatively wide range of intentional variation in the frequency. Interleaved operation of parallel PWM receiver circuits are utilized in some embodiments. In one embodiment currents are integrated during low and high portions of the duty cycle of the PWM data signal and the difference in the respective voltages generated through such integration used to demodulate the PWM data signal.
Abstract translation: PWM接收器电路接收和解调脉宽调制（PWM）数据信号而不需要同步，使得不需要向PWM数据信号提供同步前同步码。 实施例可以消耗更少的功率，因为不需要将PLL，计数器或其他电路重复同步到PWM数据信号。 此外，PWM接收器电路在PWM信号的频率中考虑到或者“容忍”抖动以及频率的有意变化的相对宽的范围。 在一些实施例中，采用并行PWM接收器电路的交织操作。 在一个实施例中，在PWM数据信号的占空比的低和高部分集成电流，并且通过这样的积分产生的各个电压的差用于解调PWM数据信号。
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5.发明申请公开(公告)号：US20150280898A1
公开(公告)日：2015-10-01
申请号：US14231499
申请日：2014-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
Abstract translation: 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。
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Patent Agency Ranking
公开(公告)号：US09832008B2
公开(公告)日：2017-11-28
申请号：US14986152
申请日：2015-12-31
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
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公开(公告)号：US09696351B2
公开(公告)日：2017-07-04
申请号：US14585357
申请日：2014-12-30
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Daljeet Kumar , Tapas Nandy , Surendra Kumar
CPC classification number: G01R19/04 , G01R19/2503
Abstract: A data receiving device may include an envelope detector that may include first and second inputs configured to receive a differential input signal, a first pair of detectors coupled to the first input and configured to generate first and second detector outputs, and a second pair of detectors coupled to the second input and configured to generate third and fourth detector outputs. The envelope detector may also include a logic circuit configured to generate a reset based upon the first and third detectors. The data receiving device may also include a receiver circuit coupled to the envelope detector and configured to generate an output based upon the second and fourth detectors along with the reset, and a first bit detection circuit coupled to the receiver circuit.
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公开(公告)号：US20170005780A1
公开(公告)日：2017-01-05
申请号：US14788721
申请日：2015-06-30
Applicant: STMicroelectronics International N.V.
Inventor： Tapas Nandy , Nitin Gupta
IPC: H04L7/00
CPC classification number: H04L7/0008 , G06F1/10 , H04J3/0685 , H04L1/0026 , H04L5/00 , H04L7/02 , H04L7/027 , H04L7/033 , H04L7/0337
Abstract: A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
Abstract translation: 源同步数据传输系统包括数据发送装置和数据接收装置。 专用数据线将数据信号从数据传输装置传送到数据接收装置。 专用时钟线将数据传输装置的调制时钟信号传送到数据接收装置。 数据传输装置包括：时钟数据驱动器，被配置为通过调制调制时钟信号的幅度将数据编码成调制时钟信号。 因此，源同步数据传输系统的时钟线携带时钟信号和附加数据。
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9.发明授权Oversampling CDR which compensates frequency difference without elasticity buffer 有权过采样CDR，补偿频率差，无弹性缓冲公开(公告)号：US09356770B2
公开(公告)日：2016-05-31
申请号：US14231499
申请日：2014-03-31
Applicant: STMicroelectronics International N.V.
Inventor： Abhishek Chowdhary , Vivek Uppal , Alok Kaushik , Sajal Kumar Mandal , Tapas Nandy , Sanjeev Chopra
CPC classification number: H04L7/0087 , H03L7/0807 , H03L7/091 , H04L7/0004 , H04L7/005 , H04L7/033 , H04L7/0331 , H04L7/0338 , H04L25/03057 , H04L43/022
Abstract: A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.
Abstract translation: 补偿过采样CDR中的频率差的方法，算法，架构，电路和/或系统。 过采样的CDR使用可编程分频器，其分频比从其通常的分频比改变一个或多个周期，当任一方向上的累积相位移动超过阈值时。 因此，过采样CDR中的弹性缓冲器可以被制造得更小或完全消除，导致较少的面积，并且减少或消除了最大允许突发尺寸对ppm差的依赖性。 门限可以保持可编程，并且超过一半单位间隔，以提供对高频抖动的鲁棒性。
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10.发明授权Automatic power switching and power harvesting in thin oxide open drain transmitter circuits, systems, and methods 有权薄氧化物开漏发射器电路，系统和方法中的自动功率开关和功率采集公开(公告)号：US09331671B2
公开(公告)日：2016-05-03
申请号：US14283043
申请日：2014-05-20
Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
Inventor： Nitin Gupta , Paramjeet Singh Sahni , Tapas Nandy , Manish Garg
CPC classification number: H03K3/01 , H03K19/018528 , H04N5/44 , H04N5/63
Abstract: A power harvesting circuit includes a new transmitter topology that ensures that no junction of thin oxide transistors forming the power harvesting circuit will experience a voltage across junctions of the transistors that is more than a maximum tolerable junction voltage. A supplemental power feed circuit operates to provide a supplemental feed current to components in a transmitter circuit when power harvested from a receiver circuit is insufficient to adequately power these components of the transmitter circuit, which may occur during high frequency operation of communications channels coupling the transmitter and receiver circuits. The supplemental power feed circuit also operates to sink a shunt current when power harvested from the receiver circuit is more than is needed to power the components in the transmitter circuit.
Abstract translation: 功率收集电路包括新的发射机拓扑结构，其确保形成功率收集电路的薄氧化物晶体管的结不会经受超过最大可容忍结电压的晶体管结的电压。 补充供电电路用于在从接收器电路收集的功率不足以对发射机电路的这些组件充分供电时，向发射机电路中的组件提供补充馈电电流，这可能在耦合发射机的通信信道的高频操作期间发生 和接收器电路。 当从接收器电路收集的功率大于为发射机电路中的组件供电所需的功率时，辅助馈电电路还用于吸收分流电流。
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