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公开(公告)号：US20210249086A1
公开(公告)日：2021-08-12
申请号：US17166107
申请日：2021-02-03
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
Abstract: The memory device of the electrically-erasable programmable read-only memory type comprises write circuitry designed to carry out a write operation in response to receiving a command for writing at least one selected byte in at least one selected memory word of the memory plane, the write operation comprising an erase cycle followed by a programming cycle, and configured for generating, during the erase cycle, an erase voltage in the memory cells of all the bytes of the at least one selected memory word, and an erase inhibit potential configured, with respect to the erase voltage, for preventing the erasing of the memory cells of the non-selected bytes of the at least one selected memory word, which are not the at least one selected byte.
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公开(公告)号：US10675881B2
公开(公告)日：2020-06-09
申请号：US16220476
申请日：2018-12-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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公开(公告)号：US20190067307A1
公开(公告)日：2019-02-28
申请号：US16057193
申请日：2018-08-07
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
IPC: H01L27/11526 , G11C16/04 , G11C16/14 , G11C16/10
CPC classification number: H01L27/11526 , G11C5/025 , G11C16/0433 , G11C16/06 , G11C16/10 , G11C16/14 , H01L27/11524 , H01L27/11529
Abstract: A memory device includes a memory plane including a succession of neighboring semiconductor recesses of a first type of conductivity, wherein each semiconductor recess houses a plurality of memory words including a plurality of memory cells, wherein each memory cell includes a state transistor having a floating gate and a control gate. The memory device further includes a plurality of control gate selection transistors respectively allocated to each memory word of the plurality of memory words, wherein each control gate selection transistor is coupled to the control gates of the state transistors of the memory word to which the control gate selection transistor is allocated, wherein each control gate selection transistor is situated in and on a neighbor semiconductor recess of the semiconductor recess housing the memory word to which the control gate selection transistor is allocated.
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公开(公告)号：US09728248B2
公开(公告)日：2017-08-08
申请号：US14657914
申请日：2015-03-13
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
IPC: G11C11/41 , G11C11/412 , G11C14/00 , G11C16/04 , H01L27/11
CPC classification number: G11C11/41 , G11C11/4125 , G11C14/0054 , G11C14/0063 , G11C16/0416 , H01L23/5226 , H01L27/1104 , H01L29/0847 , H01L29/42364 , H01L29/513 , H01L29/518 , H01L29/788
Abstract: A semiconductor structure includes first and second source/drain region disposed in a semiconductor body and spaced from each other by a channel region. A gate electrode overlies the channel region and a capacitor electrode is disposed between the gate electrode and the channel region. A first gate dielectric is disposed between the gate electrode and the capacitor electrode and a second gate dielectric disposed between the capacitor electrode and the channel region. A first electrically conductive contact region is in electrical contact with the gate electrode and a second electrically conductive contact region in electrical contact with the capacitor electrode. The first and second contact regions are electrically isolated from one another.
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公开(公告)号：US09472307B1
公开(公告)日：2016-10-18
申请号：US15053989
申请日：2016-02-25
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
CPC classification number: G11C29/4401 , G11C7/20 , G11C16/10 , G11C16/225 , G11C16/26 , G11C16/30 , G11C2029/0407 , G11C2029/0411
Abstract: A method can be used for checking the operation of a device of electrically erasable programmable read-only memory type powered by a power supply voltage and associated with a power on reset circuit. The method includes implementation of at least one pilot operation corresponding to a phase of operation of the device that is identified as a phase that is inclined to malfunction in the event of a drop in the power supply voltage below a given value, execution of the at least one pilot operation during the operation of the memory device, and analysis of the result of the pilot operation so as to detect any malfunction not prevented by the reset circuit.
Abstract translation: 一种方法可用于检查由电源电压供电并与上电复位电路相关联的电可擦除可编程只读存储器类型的装置的操作。 该方法包括实现对应于被识别为在电源电压低于给定值的情况下倾向于故障的相位的装置的操作相位的至少一个导频操作，执行at 在存储装置的操作期间的至少一个导频操作，以及导频操作的结果的分析，以便检测不被复位电路防止的任何故障。
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Patent Agency Ranking
公开(公告)号：US20160173171A1
公开(公告)日：2016-06-16
申请号：US14849385
申请日：2015-09-09
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
CPC classification number: H04B5/0037 , G06K19/07769 , H02H9/044
Abstract: An electronic device includes at least one processing circuit connected through at least one terminal at a first reference voltage. At least one radio frequency communication circuit is connected at least to receive the reference voltage. At least one first pad is intended to be taken to a second reference voltage of at least one electronic circuit external to the device. At least one first resistive impedance is coupled between the terminal and the first pad.
Abstract translation: 电子设备包括至少一个处理电路，其通过至少一个终端以第一参考电压连接。 至少一个射频通信电路至少连接以接收参考电压。 至少一个第一焊盘旨在被带到设备外部的至少一个电子电路的第二参考电压。 至少一个第一电阻阻抗耦合在端子和第一焊盘之间。
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7.发明授权Compact memory device including a SRAM memory plane and a non volatile memory plane, and operating methods 有权包括SRAM存储器平面和非易失性存储器平面的紧凑型存储器件以及操作方法公开(公告)号：US09245627B2
公开(公告)日：2016-01-26
申请号：US14296014
申请日：2014-06-04
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
IPC: G11C14/00 , G11C16/04 , G11C5/02 , G11C16/20 , G11C11/404
CPC classification number: G11C16/0408 , G11C11/404 , G11C14/0018 , G11C14/0063 , G11C16/20
Abstract: A memory device includes a memory cell with an elementary SRAM-type cell and an elementary module coupled between a supply terminal and the elementary SRAM-type cell. The elementary module has a single nonvolatile EEPROM elementary memory cell that includes a floating gate transistor. The elementary module also has a controllable interconnection stage that can be controlled by a control signal external to the memory cell. The nonvolatile elementary memory cell and the controllable interconnection stage are connected to one another. The floating gate transistor of the nonvolatile memory cell is controllable to be turned off when a data item stored in the elementary SRAM-type cell is programmed into the nonvolatile elementary cell.
Abstract translation: 存储器件包括具有基本SRAM型单元的存储单元和耦合在供电端和基本SRAM型单元之间的基本模块。 基本模块具有包括浮栅晶体管的单个非易失性EEPROM单元存储单元。 基本模块还具有可控制的互连级，其可以由存储器单元外部的控制信号控制。 非易失性基本存储单元和可控互连级彼此连接。 当存储在基本SRAM型单元中的数据项被编程到非易失性单元中时，非易失性存储单元的浮置栅晶体管被控制为截止。
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8.发明授权公开(公告)号：US10732894B2
公开(公告)日：2020-08-04
申请号：US15900481
申请日：2018-02-20
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista
Abstract: A method of writing in a memory of the EEPROM type includes, in the presence of a string of new bytes to be written in the memory plane in at least one destination memory word already containing old bytes, a verification for each destination memory word whether or not the old bytes of this destination memory word must all be replaced with new bytes. The method also includes a reading of the old bytes of this destination memory word only if the old bytes must not all be replaced with new bytes.
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公开(公告)号：US20190118544A1
公开(公告)日：2019-04-25
申请号：US16220476
申请日：2018-12-14
Applicant: STMicroelectronics (Rousset) SAS
Inventor： François Tailliet , Marc Battista , Victorien Brecte
IPC: B41J2/175
CPC classification number: B41J2/17556 , B41J2/175 , B41J2/17523 , B41J2/17596 , G11C7/067 , G11C16/0433 , G11C16/24 , G11C16/26
Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.
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10.发明申请公开(公告)号：US20180294030A1
公开(公告)日：2018-10-11
申请号：US16010268
申请日：2018-06-15
Applicant: STMicroelectronics (Rousset) SAS
Inventor： Francois Tailliet , Marc Battista
IPC: G11C13/00
CPC classification number: G11C13/0097 , G11C5/144 , G11C13/0069 , G11C16/10 , G11C16/14 , G11C16/30 , G11C16/32 , G11C16/3418 , G11C29/12005
Abstract: A method of controlling a cycle for writing at least one data item to at least one memory slot of the electrically programmable and erasable read-only memory type disposed in an electronic circuit supplied by a supply voltage includes a controlled increase of the duration of the write cycle in the presence of a decrease in the supply voltage.
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