公开(公告)号：US20240047539A1

公开(公告)日：2024-02-08

申请号：US17984025

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ming He ,  Mehdi Saremi ,  Rebecca Park ,  Muhammed Ahosan Ul Karim ,  Harsono Simka ,  Sungil Park ,  Myungil Kang ,  Kyungho Kim ,  Doyoung Choi ,  JaeHyun Park

IPC: H01L29/417 ,  H01L29/10 ,  H01L29/20 ,  H01L29/66 ,  H01L29/808

CPC classification number: H01L29/41791 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/6681 ,  H01L29/8083

Abstract: Provided is a three-dimensionally stacked field-effect transistor (3DSFET) device which includes: a lower source/drain region of a 1st polarity type connected to a lower channel structure; an upper source/drain region of a 2nd polarity type, connected to an upper channel structure, above the lower source/drain region; and a PN junction structure, between the lower source/drain region and the upper source/drain region, configured to electrically isolate the upper source/drain region from the lower source/drain region, wherein the PN junction structure includes a 1st region of the 1st polarity type and a 2nd region of the 2nd polarity type.

公开(公告)号：US20230020176A1

公开(公告)日：2023-01-19

申请号：US17840819

申请日：2022-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeseoung Park ,  Wandon Kim ,  Suyoung Bae ,  Dongsoo Lee ,  Dongsuk Shin ,  Doyoung Choi

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/49 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.

公开(公告)号：US12262558B2

公开(公告)日：2025-03-25

申请号：US17840819

申请日：2022-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeseoung Park ,  Wandon Kim ,  Suyoung Bae ,  Dongsoo Lee ,  Dongsuk Shin ,  Doyoung Choi

IPC: H10D84/85 ,  H01L21/02 ,  H10D30/01 ,  H10D30/67 ,  H10D30/69 ,  H10D62/10 ,  H10D64/01 ,  H10D84/01 ,  H10D84/03

Abstract: A semiconductor device includes a substrate including first and second regions, first and second active patterns provided on the first and second regions, respectively, a pair of first source/drain patterns on the first active pattern and a first channel pattern therebetween, a pair of second source/drain patterns on the second active pattern and a second channel pattern therebetween, first and second gate electrodes respectively provided on the first and second channel patterns, and first and second gate insulating layers respectively interposed between the first and second channel patterns and the first and second gate electrodes. Each of the first and second gate insulating layers includes an interface layer and a first high-k dielectric layer thereon, and the first gate insulating layer further includes a second high-k dielectric layer on the first high-k dielectric layer.

公开(公告)号：US11158716B2

公开(公告)日：2021-10-26

申请号：US16901207

申请日：2020-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Nakjin Son ,  Seungjoon Lee ,  Bong Seob Yang ,  Doyoung Choi

IPC: H01L29/49 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/51 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device include a substrate including a peripheral region, a first active pattern provided on the peripheral region of the substrate, the first active pattern having an upper portion including first semiconductor patterns and second semiconductor patterns which are alternately stacked, a first gate electrode intersecting the first active pattern, a pair of first source/drain patterns provided at both sides of the first gate electrode, respectively, and a first gate insulating layer disposed between the first gate electrode and the first active pattern. The first gate insulating layer includes a first insulating layer formed on the first active pattern, a second insulating layer formed on the first insulating layer, and a high-k dielectric layer formed on the second insulating layer. The first gate insulating layer contains a first dipole element including lanthanum (La), aluminum (Al), or a combination thereof.

公开(公告)号：US20240145544A1

公开(公告)日：2024-05-02

申请号：US18482154

申请日：2023-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungho Kim ,  Myungil Kang ,  Kyunghee Cho ,  Doyoung Choi ,  Donghoon Hwang

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H10B10/00

CPC classification number: H01L29/0673 ,  H01L29/0847 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78645 ,  H01L29/78696 ,  H10B10/125

Abstract: A semiconductor device includes an active pattern extending in a first direction; a plurality of channel layers spaced apart from each other on the active pattern in a vertical direction and including lower channel layers and upper channel layers; an intermediate insulating layer between an uppermost lower channel layer and a lowermost upper channel layer; a gate structure intersecting the active pattern and the plurality of channel layers, and extending in a second direction intersecting the first direction; a lower source/drain region on a first side of the gate structure and connected to the lower channel layers; a blocking structure on a second side of the gate structure and connected to the lower channel layers; and an upper source/drain region on at least one side of the gate structure.

公开(公告)号：US20230046546A1

公开(公告)日：2023-02-16

申请号：US17699724

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Jae Hyun Park ,  Doyoung Choi ,  Youngmoon Choi ,  Daewon Ha

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

公开(公告)号：US20250107178A1

公开(公告)日：2025-03-27

申请号：US18643104

申请日：2024-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghee Cho ,  Donghoon Hwang ,  Hyojin Kim ,  Byungho Moon ,  Doyoung Choi

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: An integrated circuit device includes a first fin and a second fin that extend in a first horizontal direction on a first region of a substrate, a third fin and a fourth fin that extend in the first horizontal direction on a second region of a substrate, a connected gate line at least partially surrounding a first channel region and a second channel region, and a separated gate line including a first separated portion that at least partially surrounds a third channel region and a second separated portion that at least partially surrounds a fourth channel region, where an uppermost portion of a top surface of the separated gate line is at a first vertical level, and an uppermost portion of a top surface of the connected gate line is at a second vertical level higher than the first vertical level.

公开(公告)号：US12255206B2

公开(公告)日：2025-03-18

申请号：US17699724

申请日：2022-03-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungil Park ,  Jae Hyun Park ,  Doyoung Choi ,  Youngmoon Choi ,  Daewon Ha

IPC: H01L27/092 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device includes: an active pattern extending in a first direction on a substrate; a first lower source/drain pattern and a second lower source/drain pattern provided on the active pattern and spaced apart from each other in the first direction; a first upper source/drain pattern provided on the first lower source/drain pattern; a second upper source/drain pattern provided on the second lower source/drain pattern; and a gate electrode crossing the active pattern and extending in a second direction intersecting the first direction. The gate electrode includes an overlapping portion overlapping the active pattern in a third direction perpendicular to the first direction and the second direction. A length of the overlapping portion in the second direction is less than a length of the first lower source/drain pattern in the second direction.

公开(公告)号：US10043873B2

公开(公告)日：2018-08-07

申请号：US15060174

申请日：2016-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyoung Hwan Yeo ,  Seonguk Park ,  Seungjae Lee ,  Doyoung Choi ,  Sunhom Steve Paak ,  Tae Eung Yoon ,  Dongho Cha ,  Ruiyi Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/40 ,  H01L29/66 ,  H01L27/11 ,  H01L29/417 ,  H01L29/78

Abstract: Provided is a semiconductor device with a field effect transistor. The semiconductor device includes a substrate, an active pattern on the substrate, a gate electrode crossing the active pattern and a capping structure on the gate electrode. The capping structure includes first and second capping patterns that are sequentially stacked on the gate electrode. The second capping pattern completely covers a top surface of the first capping pattern, and a dielectric constant of the second capping pattern is greater than that of the first capping pattern.

公开(公告)号：US12159939B2

公开(公告)日：2024-12-03

申请号：US17724619

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Munhyeon Kim ,  Doyoung Choi ,  Daewon Ha ,  Mingyu Kim

IPC: H01L29/786

Abstract: A semiconductor device includes an active pattern on a substrate, a plurality of source/drain patterns in a first direction on the active pattern, a first channel structure between a pair of source/drain patterns, a second channel structure between another pair of source/drain patterns, a first gate electrode extending in a second direction perpendicular to the first direction, and a second gate electrode intersecting the second channel structure and extending in the second direction. The first gate electrode includes a first portion between a bottom surface of the first channel structure and a top surface of the active pattern, and the second gate electrode includes a first portion between a bottom surface of the second channel structure and the top surface of the active pattern. A thickness of the first portion of the second gate electrode is greater than a thickness of the first portion of the first gate electrode.