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    NONVOLATILE MEMORY APPARATUS AND METHOD OF OPERATING THE SAME
    3.
    发明申请
    NONVOLATILE MEMORY APPARATUS AND METHOD OF OPERATING THE SAME 审中-公开
    非易失存储器装置及其操作方法

    公开(公告)号：US20140050005A1

    公开(公告)日：2014-02-20

    申请号：US13747777

    申请日：2013-01-23

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-sik CHOI ,  Ho-jung KIM ,  U-in CHUNG

    IPC: G11C7/00 ,  G11C17/00 ,  G11C11/16 ,  G11C13/00

    CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C7/1051 ,  G11C8/10 ,  G11C8/20 ,  G11C11/005 ,  G11C11/16 ,  G11C11/22 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0069 ,  G11C17/00 ,  G11C2213/79 ,  G11C2216/26

    Abstract: Nonvolatile memory apparatuses and methods of operating the same. A nonvolatile memory apparatus includes a nonvolatile memory cell array including a plurality of memory cells; an address decoder configured to receive computation data that indicates a computation from among a plurality of computations and an input data for computation, and the address decoder configured to output an address of the nonvolatile memory cell array corresponding to the indicated computation and input data, the nonvolatile memory cell array being configured to output result data stored at the output address, the result data corresponding to a previous computation performed before receipt of the computation data; and a reading unit configured to read the result data output from the nonvolatile memory cell array.

    Abstract translation: 非易失性存储装置及其操作方法。 非易失性存储装置包括：包括多个存储单元的非易失性存储单元阵列; 地址解码器，被配置为从多个计算中接收指示计算的计算数据和用于计算的输入数据，所述地址解码器被配置为输出与所指示的计算和输入数据相对应的非易失性存储单元阵列的地址， 非易失性存储单元阵列被配置为输出存储在输出地址处的结果数据，对应于在接收计算数据之前执行的先前计算的结果数据; 以及读取单元，被配置为读取从非易失性存储单元阵列输出的结果数据。

    LOGIC DEVICES, DIGITAL FILTERS AND VIDEO CODECS INCLUDING LOGIC DEVICES, AND METHODS OF CONTROLLING LOGIC DEVICES
    4.
    发明申请
    LOGIC DEVICES, DIGITAL FILTERS AND VIDEO CODECS INCLUDING LOGIC DEVICES, AND METHODS OF CONTROLLING LOGIC DEVICES 审中-公开
    逻辑设备，数字滤波器和包括逻辑设备的视频编码器以及控制逻辑设备的方法

    公开(公告)号：US20140140397A1

    公开(公告)日：2014-05-22

    申请号：US13963015

    申请日：2013-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-jung KIM ,  U-in CHUNG ,  Hyun-sik CHOI

    IPC: H04N19/593 ,  H03K19/177

    CPC classification number: H04N19/17 ,  G11C11/41 ,  G11C14/009 ,  G11C29/028 ,  H03K19/17748 ,  H03K19/17772 ,  H03K19/17776

    Abstract: A logic device includes: a function block and a configuration block. The function block is configurable to perform operations associated with a plurality of operation modes. The configuration block is configured to configure the function block to perform an operation associated with any one of the plurality of operation modes. The logic device also includes a controller configured to control the configuration block so that the function block is configured to perform the operation.

    Abstract translation: 逻辑器件包括：功能块和配置块。 功能块可配置为执行与多种操作模式相关联的操作。 配置块被配置为配置功能块以执行与多个操作模式中的任何一个相关联的操作。 逻辑设备还包括控制器，其被配置为控制配置块，使得功能块被配置为执行操作。

    POWER MODULE INCLUDING LEAKAGE CURRENT PROTECTION CIRCUIT
    5.
    发明申请
    POWER MODULE INCLUDING LEAKAGE CURRENT PROTECTION CIRCUIT 有权
    电源模块，包括泄漏电流保护电路

    公开(公告)号：US20130241604A1

    公开(公告)日：2013-09-19

    申请号：US13737217

    申请日：2013-01-09

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-jung KIM ,  Jai-kwang SHIN ,  U-in CHUNG ,  Hyun-sik CHOI

    IPC: H02H9/02 ,  H03K17/56

    CPC classification number: H02H9/02 ,  H01L2924/0002 ,  H03K17/165 ,  H03K17/56 ,  H03K2217/0036 ,  H01L2924/00

    Abstract: A power module including a power device and a periphery circuit configured to suppress a leakage current in the power device. The periphery circuit includes a leakage current detection circuit configured to detect a leakage current from the power device and control operation of the power device based on a result of the detection. The leakage current detection circuit including an input terminal connected to the power device, a plurality of NMOS transistors, a plurality of PMOS transistors connected to the plurality of NMOS transistors, and a comparator.

    Abstract translation: 一种功率模块，包括功率器件和外围电路，被配置为抑制功率器件中的漏电流。 周边电路包括漏电流检测电路，其被配置为基于检测结果检测来自功率器件的漏电流和功率器件的控制操作。 泄漏电流检测电路包括连接到功率器件的输入端子，多个NMOS晶体管，连接到多个NMOS晶体管的多个PMOS晶体管和比较器。

    LOGIC DEVICE AND OPERATING METHOD THEREOF
    8.
    发明申请
    LOGIC DEVICE AND OPERATING METHOD THEREOF 有权
    逻辑设备及其操作方法

    公开(公告)号：US20140125378A1

    公开(公告)日：2014-05-08

    申请号：US13921642

    申请日：2013-06-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ho-jung KIM ,  U-in CHUNG ,  Hyun-sik CHOI

    IPC: H03K19/173

    CPC classification number: H03K19/173 ,  G06F17/5054 ,  H03K19/17728 ,  H03K19/17736

    Abstract: A logic device includes first and second logic blocks and a connection block. Each of the first and second logic blocks configured to perform at least one function, the first logic blocks connected to first connection lines and the second logic blocks connected to second connection lines. The connection block electrically connected to the first and second logic blocks via the first connection lines and the second connection lines, respectively. The connection block including connection cells configured to select one of multiple connection configurations between the first connection lines and the second connection lines based on a desired function.

    Abstract translation: 逻辑设备包括第一和第二逻辑块和连接块。 被配置为执行至少一个功能的第一和第二逻辑块中的每一个，连接到第一连接线的第一逻辑块和连接到第二连接线的第二逻辑块。 连接块分别经由第一连接线和第二连接线电连接到第一和第二逻辑块。 所述连接块包括被配置为基于所需功能在所述第一连接线和所述第二连接线之间选择多个连接配置中的一个的连接单元。

    HIGH SIDE GATE DRIVER, SWITCHING CHIP, AND POWER DEVICE
    9.
    发明申请
    HIGH SIDE GATE DRIVER, SWITCHING CHIP, AND POWER DEVICE 有权
    高侧门驱动器，开关芯片和电源装置

    公开(公告)号：US20130265028A1

    公开(公告)日：2013-10-10

    申请号：US13688484

    申请日：2012-11-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyun-sik CHOI ,  Ho-jung KIM ,  Jai-kwang SHIN ,  U-in CHUNG

    IPC: H03K3/00 ,  G05F3/02

    CPC classification number: H03K3/00 ,  G05F3/02 ,  H01L2924/0002 ,  H03K17/06 ,  H01L2924/00

    Abstract: A high side gate driver, a switching chip, and a power device, which respectively include a protection device, are provided. The high side gate driver includes a first terminal configured to receive a first low level driving power supply that is provided to turn off the high side normally-on switch; a first switching device connected to the first terminal; and a protection device connected in series between the first switching device and a gate of the high side normally-on switch, the protection device configured to absorb a majority of a voltage applied to a gate of the high side normally-on switch. The power device includes the high side gate driver. In addition, the switching chip includes a high side normally-on switch, an additional normally-on switch, and a low side normally-on switch, which have a same structure.

    Abstract translation: 提供分别包括保护装置的高侧栅极驱动器，开关芯片和功率器件。 高侧栅极驱动器包括：第一端子，被配置为接收被提供以关闭高侧常开开关的第一低电平驱动电源; 连接到第一端子的第一开关装置; 以及保护装置，串联连接在第一开关装置和高侧常开开关的栅极之间，保护装置被配置为吸收施加到高侧常开开关的栅极的电压的大部分。 功率器件包括高边栅驱动器。 此外，开关芯片包括具有相同结构的高边常开开关，附加常开开关和低边常开开关。

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