公开(公告)号：US10304781B2

公开(公告)日：2019-05-28

申请号：US15459917

申请日：2017-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-gyu Baek ,  Yun-rae Cho ,  Hyung-gil Baek ,  Sun-dae Kim

IPC: H01L23/58 ,  H01L23/00 ,  H01L21/66

Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

公开(公告)号：US20170317035A1

公开(公告)日：2017-11-02

申请号：US15448215

申请日：2017-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-dae Kim ,  Hyung-gil Baek ,  Yun-rae Cho ,  Nam-gyu Baek

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/58 ,  H01L21/78

CPC classification number: H01L23/562 ,  H01L21/78 ,  H01L23/585 ,  H01L2224/16225 ,  H01L2924/181 ,  H01L2924/00012

Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

公开(公告)号：US10008462B2

公开(公告)日：2018-06-26

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L21/00 ,  H01L23/00 ,  H01L23/31 ,  H01L23/29

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

公开(公告)号：US20170084558A1

公开(公告)日：2017-03-23

申请号：US15226231

申请日：2016-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung Seo ,  Tae-je Cho ,  Yong-hwan Kwon ,  Hyung-gil Baek ,  Hyun-soo Chung ,  Seung-kwan Ryu ,  Myeong-soon Park

IPC: H01L23/00 ,  H01L23/29 ,  H01L23/31

CPC classification number: H01L24/08 ,  H01L23/291 ,  H01L23/3171 ,  H01L24/02 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/94 ,  H01L2224/02311 ,  H01L2224/02321 ,  H01L2224/0235 ,  H01L2224/02351 ,  H01L2224/0236 ,  H01L2224/0239 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05011 ,  H01L2224/05012 ,  H01L2224/05014 ,  H01L2224/05015 ,  H01L2224/05017 ,  H01L2224/05082 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05558 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/08058 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/94 ,  H01L2924/19105 ,  H01L2224/11 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/01046 ,  H01L2924/01083 ,  H01L2924/01051 ,  H01L2224/034 ,  H01L2224/1146 ,  H01L2224/0361 ,  H01L2924/01028 ,  H01L2924/01079 ,  H01L2924/01024 ,  H01L2924/01022

Abstract: A semiconductor package includes a semiconductor substrate and an electrode pad formed on the semiconductor substrate. The electrode pad includes a central portion and a peripheral portion, and a first pattern is located on the peripheral portion. A passivation layer is formed on the semiconductor substrate and the electrode pad. The passivation layer has an opening exposing the central portion of the electrode pad and a second pattern located on the first pattern. A seed layer is formed on the electrode pad and the passivation layer. The seed layer has a third pattern formed on the second pattern. A bump is formed on the seed layer and electrically connected to the electrode pad. An undercut is formed around the third pattern located under an edge of a lower portion of the bump.

公开(公告)号：US10103109B2

公开(公告)日：2018-10-16

申请号：US15448215

申请日：2017-03-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-dae Kim ,  Hyung-gil Baek ,  Yun-rae Cho ,  Nam-gyu Baek

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/78

Abstract: Provided is a semiconductor device including a semiconductor substrate including a main chip area and a scribe lane area adjacent to the main chip area, the scribe lane area including a first region adjacent to the main chip area and a second region adjacent to the first region; an insulating layer disposed on the semiconductor substrate; first embossing structures disposed on a first surface of the insulating layer in a first area of the insulating layer corresponding to the first region; second embossing structures disposed on the first surface of the insulating layer in a second area of the insulating layer corresponding to the second region; and dam structures provided in the first area of the insulating layer at positions corresponding to the first embossing structures, the dam structures extending in a direction perpendicular to a second surface of the insulating layer that is adjacent to the semiconductor substrate.

公开(公告)号：US20170345773A1

公开(公告)日：2017-11-30

申请号：US15459917

申请日：2017-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-gyu BAEK ,  Yun-rae Cho ,  Hyung-gil Baek ,  Sun-dae Kim

IPC: H01L23/00 ,  H01L23/58 ,  H01L21/66

CPC classification number: H01L23/562 ,  H01L22/34 ,  H01L23/585

Abstract: The semiconductor devices may include a semiconductor substrate, and a guard ring and a crack sensing circuit on the semiconductor substrate. The semiconductor substrate may include a main chip region that is defined by the guard ring and includes the crack sensing circuit, a central portion of the main chip region surrounded by the crack sensing circuit, and a chamfer region that is in a corner portion of the main chip region and is defined by the guard ring and the crack sensing circuit. The semiconductor devices may also include at least one gate structure on the semiconductor substrate in the main chip region, a plurality of metal pattern structures on the at least one gate structure in the chamfer region, and an insulating layer on the plurality of metal pattern structures. The plurality of metal pattern structures may extend in parallel to one another and may have different lengths.

公开(公告)号：US09775230B2

公开(公告)日：2017-09-26

申请号：US15232794

申请日：2016-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-jae Kim ,  Hyung-gil Baek ,  Baik-woo Lee

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/40 ,  H05K3/22

CPC classification number: H05K1/0219 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/183 ,  H05K3/0073 ,  H05K3/22 ,  H05K3/3452 ,  H05K3/4007 ,  H05K2201/0373 ,  H05K2201/0376 ,  H05K2201/09409 ,  H05K2201/09745 ,  H05K2201/0989 ,  H05K2203/1105 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A printed circuit board is provided. The printed circuit board comprises a base substrate comprising a chip mounting region on an upper surface thereof, a plurality of connection pad structures in the chip mounting region, and an extension pattern on the base substrate, spaced from each of two adjacent connection pad structures from among the plurality of connection pad structures, and extending along the two adjacent connection pad structures. Upper surfaces of the plurality of connection pad structures are positioned at a higher level than an upper surface of the extension pattern.