公开(公告)号：US08759967B2

公开(公告)日：2014-06-24

申请号：US14013238

申请日：2013-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hak-Kyoon Byun ,  Dae-Young Choi ,  Mi-Yeon Kim

IPC: H01L23/02 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract translation: 提供半导体封装和封装封装。 半导体封装包括衬底; 安装在所述基板的表面上的半导体芯片; 设置在基板的表面上的连接导体; 形成在所述基板上并且设置有所述连接导体和所述半导体芯片的模具; 并且连接通过模具延伸的通孔并暴露连接导体。 对于连接通孔的第一连接通孔，由第一连接通孔露出的第一连接导体与第一连接通孔的入口之间的平面距离不均匀。

公开(公告)号：US09111926B2

公开(公告)日：2015-08-18

申请号：US14289635

申请日：2014-05-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Kyoon Byun ,  Dae-Young Choi ,  Mi-Yeon Kim

IPC: H01L23/02 ,  H01L23/48 ,  H01L23/498 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.

Abstract translation: 提供半导体封装和封装封装。 半导体封装包括衬底; 安装在所述基板的表面上的半导体芯片; 设置在基板的表面上的连接导体; 形成在所述基板上并且设置有所述连接导体和所述半导体芯片的模具; 并且连接通过模具延伸的通孔并暴露连接导体。 对于连接通孔的第一连接通孔，由第一连接通孔露出的第一连接导体与第一连接通孔的入口之间的平面距离不均匀。

公开(公告)号：US09190401B2

公开(公告)日：2015-11-17

申请号：US14286454

申请日：2014-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Choong-Bin Yim ,  Seung-Kon Mok ,  Jin-Woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L25/50 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Semiconductor package includes a first semiconductor package including a first printed circuit board, and a first semiconductor device mounted on the first printed circuit board, and a second semiconductor package stacked on the first semiconductor package, and including a second printed circuit board and a second semiconductor device mounted on the second printed circuit board. The semiconductor package includes at least one first through electrode electrically connecting the second semiconductor package to the first printed circuit board through the first semiconductor device.

Abstract translation: 半导体封装包括第一半导体封装，包括第一印刷电路板和安装在第一印刷电路板上的第一半导体器件，以及堆叠在第一半导体封装上的第二半导体封装，并且包括第二印刷电路板和第二半导体 装置安装在第二印刷电路板上。 半导体封装包括至少一个第一通孔，其通过第一半导体器件将第二半导体封装电连接到第一印刷电路板。

公开(公告)号：US08970025B2

公开(公告)日：2015-03-03

申请号：US14279776

申请日：2014-05-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hun Kim ,  Jin-Woo Park ,  Dae-Young Choi ,  Mi-Yeon Kim ,  Sun-Hye Lee

IPC: H01L23/02 ,  H01L21/00 ,  H01L23/522 ,  H01L25/10 ,  H01L25/16 ,  H01L21/78 ,  H01L23/48 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/5226 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/14 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/11 ,  H01L2924/00012

Abstract: Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.

Abstract translation: 提供了一种形成封装封装的方法。 使用晶片级成型工艺形成覆盖晶片的封装。 晶片包括多个半导体芯片和穿过半导体芯片的多个通孔硅通孔（TSV）。 密封剂可以具有与TSV对准的开口。 密封剂和半导体芯片被分割以形成多个半导体封装。 另一个半导体封装堆叠在从半导体封装中选择的一个上。 另一个半导体封装电连接到TSV。

公开(公告)号：US20140001649A1

公开(公告)日：2014-01-02

申请号：US14013238

申请日：2013-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hak-Kyoon Byun ,  Dae-Young Choi ,  Mi-Yeon Kim

IPC: H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.