公开(公告)号：US20220216227A1

公开(公告)日：2022-07-07

申请号：US17539523

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangho RHA ,  Iksoo KIM ,  Jiwoon IM ,  Byungsun PARK ,  Seonkyu SHIN

IPC: H01L27/11556 ,  H01L27/11582 ,  G11C5/06 ,  G11C5/02 ,  H01L29/423

Abstract: A semiconductor device includes a memory cell structure on a substrate, and a dummy structure on a side of the memory cell structure. The memory cell structure includes a memory stack structure including interlayer insulating layers and gate electrodes alternately stacked on the substrate, channel structures penetrating through the memory stack structure and contacting the substrate, and first separation structures penetrating through the memory stack structure and extending in the first direction to separate the gate electrodes from each other in a second direction. The dummy structure includes dummy stack structures spaced apart from the memory stack structure and including first insulating layers and dummy gate electrodes alternately stacked, dummy channel structures penetrating through the dummy stack structures, and second separation structures penetrating through the dummy stack structures and extending in the second direction to separate the dummy gate electrodes from each other in the first direction.

公开(公告)号：US20240213017A1

公开(公告)日：2024-06-27

申请号：US18228220

申请日：2023-07-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younghun SUNG ,  Sunhye HWANG ,  Sangho RHA ,  Seungjae SIM ,  Younseok CHOI ,  Byungkeun HWANG ,  Youn Joung CHO

IPC: H01L21/02 ,  C23C16/34 ,  C23C16/40 ,  C23C16/50 ,  C23C16/56 ,  H01L21/311

CPC classification number: H01L21/02164 ,  C23C16/345 ,  C23C16/401 ,  C23C16/50 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/31116 ,  H10B43/27

Abstract: A method of manufacturing an integrated circuit device, the method including forming a doped silicon oxide film on a substrate by supplying, onto the substrate, a silicon precursor, an oxidant, and at least two dopant sources including dopant elements that are different from each other such that the doped silicon oxide film includes at least two dopant elements; forming a vertical hole in the doped silicon oxide film by dry-etching the doped silicon oxide film; and forming a vertical structure in the vertical hole, wherein the silicon precursor includes a monosilane compound, a disilane compound, a siloxane compound, or a combination thereof, and the silicon precursor includes a Si—H functional group, and a C1-C10 oxy group or a C1-C10 organoamino group.

公开(公告)号：US20170092578A1

公开(公告)日：2017-03-30

申请号：US15375567

申请日：2016-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongmin BAEK ,  Sangho RHA ,  Sanghoon AHN ,  Wookyung YOU ,  Naein LEE

IPC: H01L23/528 ,  H01L23/532

CPC classification number: H01L23/528 ,  H01L21/7682 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. A semiconductor device includes gaps between conductive patterns. Moreover, the semiconductor device includes a permeable layer on the conductive patterns. Methods of fabricating semiconductor devices are also provided.

公开(公告)号：US20250137131A1

公开(公告)日：2025-05-01

申请号：US18670957

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minju LEE ,  Daihong KIM ,  Sangho RHA ,  Juchan BANG ,  Seungjae SIM ,  Mingyu JEON

IPC: C23C16/458 ,  C23C16/455 ,  C23C16/56

Abstract: A deposition apparatus includes: a chamber; a support unit within the chamber and including a chuck and a driving member, wherein a substrate is seated on the chuck, wherein the chuck has a first process position and a second process position, wherein the first process position is for processing the substrate in a first process, wherein the second process position is for processing the substrate in a second process, wherein the driving member moves the chuck between the first process position and the second process position; a showerhead supplying process gas toward the substrate, when the chuck is located in the first process position; a power supply unit supplying power to generate plasma between the chuck and the showerhead; and a first ultraviolet lamp disposed in the chamber and emitting ultraviolet rays toward the substrate, when the chuck is located in the second process position.

公开(公告)号：US20220136108A1

公开(公告)日：2022-05-05

申请号：US17577204

申请日：2022-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Sun PARK ,  Ik Soo KIM ,  Jiwoon IM ,  Sangho RHA ,  Minjae OH

IPC: C23C16/455 ,  H01L21/67 ,  H01J37/32

Abstract: A semiconductor manufacturing apparatus includes a chamber that includes a station in which a substrate is provided, a substrate holder that is in the station and receives the substrate, and lower showerheads below the substrate holder, the lower showerheads including an isotropic showerhead having first nozzle holes that isotropically provide a first reaction gas on a bottom surface of the substrate, and a striped showerhead having striped nozzle regions and striped blank regions between the striped nozzle regions, the striped nozzle regions having second nozzle holes that non-isotropically provide a second reaction gas on the bottom surface of the substrate.

公开(公告)号：US20200325579A1

公开(公告)日：2020-10-15

申请号：US16750557

申请日：2020-01-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Sun PARK ,  Ik Soo KIM ,  Jiwoon IM ,  Sangho RHA ,  Minjae OH

IPC: C23C16/455 ,  H01J37/32 ,  H01L21/67

Abstract: A semiconductor manufacturing apparatus includes a chamber that includes a station in which a substrate is provided, a substrate holder that is in the station and receives the substrate, and lower showerheads below the substrate holder, the lower showerheads including an isotropic showerhead having first nozzle holes that isotropically provide a first reaction gas on a bottom surface of the substrate, and a striped showerhead having striped nozzle regions and striped blank regions between the striped nozzle regions, the striped nozzle regions having second nozzle holes that non-isotropically provide a second reaction gas on the bottom surface of the substrate.

公开(公告)号：US20190206794A1

公开(公告)日：2019-07-04

申请号：US16296388

申请日：2019-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangho RHA ,  Jongmin BAEK ,  Wookyung YOU ,  Sanghoon AHN ,  Nae-In LEE

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/522 ,  H01L21/306 ,  H01L21/288 ,  H01L23/532 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L23/5283 ,  H01L21/02178 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76871 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of forming a semiconductor device are provided. A method of forming a semiconductor device may include forming a capping layer on a metal pattern and on an adjacent portion of an insulating layer, the capping layer comprising a first etch selectivity, with respect to the insulating layer, on the metal pattern and a second etch selectivity, with respect to the insulating layer, on the portion of the insulating layer. Moreover, the method may include forming a recess region adjacent the metal pattern by removing the capping layer from the portion of the insulating layer. At least a portion of the capping layer may remain on an uppermost surface of the metal pattern after removing the capping layer from the portion of the insulating layer. Related semiconductor devices are also provided.