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    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices 有权

    公开(公告)号：US10573356B2

    公开(公告)日：2020-02-25

    申请号：US15851197

    申请日：2017-12-21

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Young-Hun Seo ,  Kwang-Il Park ,  Seung-Jun Bae

    IPC: G06F11/00 ,  G11C7/10 ,  G11C11/4093 ,  G11C11/4096 ,  H03M13/00 ,  G06F11/10

    Abstract: A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, an input/output (I/O) gating circuit and a control logic circuit. The memory cell array includes bank arrays, each of the bank arrays includes a first sub array and a second sub array, and each of the first sub array and the second sub array includes a normal cell region to store data bits and a parity cell region to store parity bits. The ECC engine generates the parity bits and corrects error bit. The I/O gating circuit is connected between the ECC engine and the memory cell array. The control logic circuit controls the I/O gating circuit to perform column access to the normal cell region according to a multiple of a burst length and to perform column access to the parity cell region according to a non-multiple of the burst length partially.

    Circuit and method for on-die termination, and semiconductor memory device including the same
    2.
    发明授权
    Circuit and method for on-die termination, and semiconductor memory device including the same 有权
    用于片上端接的电路和方法，以及包括其的半导体存储器件

    公开(公告)号：US09264039B2

    公开(公告)日：2016-02-16

    申请号：US14202323

    申请日：2014-03-10

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Young-Soo Sohn ,  Ho-Sung Song

    IPC: H03K17/16 ,  H03K19/003 ,  H03K19/00

    CPC classification number: H03K19/0005

    Abstract: An on-die termination (ODT) circuit includes a calibration unit, an offset-code generating unit, an adder, and an ODT unit. The calibration unit generates a pull-up code and a pull-down code. The offset-code generates a pull-up offset code and a pull-down offset code based on a mode-register-set signal, the pull-up code, and the pull-down code. The adder adds the pull-up offset code and the pull-down offset code to the pull-up code and the pull-down code, respectively, and generates a pull-up calibration code and a pull-down calibration code. The ODT unit changes ODT resistance in response to the pull-up calibration code and the pull-down calibration code.

    Abstract translation: 片上终端（ODT）电路包括校准单元，偏移码生成单元，加法器和ODT单元。 校准单元生成一个上拉代码和一个下拉代码。 偏移码基于模式寄存器设置信号，上拉代码和下拉码产生上拉偏移码和下拉偏移码。 加法器分别将上拉偏移代码和下拉偏移代码加到上拉代码和下拉代码，并产生一个上拉校准代码和一个下拉校准代码。 ODT单元根据上拉校准代码和下拉校准代码改变ODT电阻。

    Equalizer and semiconductor memory device including the same
    6.
    发明授权
    Equalizer and semiconductor memory device including the same 有权
    均衡器和包括其的半导体存储器件

    公开(公告)号：US09424897B2

    公开(公告)日：2016-08-23

    申请号：US14165990

    申请日：2014-01-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-Hyun Kim ,  Seung-Jun Bae ,  Kyung-Soo Ha

    IPC: G11C7/22 ,  H03K19/003 ,  G11C7/10 ,  H03K19/094

    CPC classification number: G11C7/22 ,  G11C7/1048 ,  G11C7/1057 ,  H03K19/00361 ,  H03K19/09429

    Abstract: Provided are an equalizer and a semiconductor memory device including the same. The equalizer includes a delay circuit and an inverting circuit. The delay circuit is configured to output, in response to a select signal, one of a delay signal delaying an input signal applied to an input/output node and an inverted signal inverting the input signal. The inverting circuit is configured to invert a signal provided from the delay circuit and output the inverted signal to the input/output node. The equalizer is configured such that when the delay circuit outputs the delay signal, the equalizer operates as an inductive bias circuit amplifying the input signal and outputting the amplified input signal, and when the delay circuit outputs the inverted signal, the equalizer operates as a latch circuit storing and outputting the input signal.

    Abstract translation: 提供了一种均衡器和包括该均衡器的半导体存储器件。 均衡器包括延迟电路和反相电路。 延迟电路被配置为响应于选择信号输出延迟施加到输入/输出节点的输入信号的延迟信号和反相输入信号的反相信号之一。 反相电路被配置为反转从延迟电路提供的信号并将反相信号输出到输入/输出节点。 均衡器被配置为使得当延迟电路输出延迟信号时，均衡器作为放大输入信号并输出​​放大的输入信号的感应偏置电路工作，并且当延迟电路输出反相信号时，均衡器作为锁存器 电路存储和输出输入信号。

    Input buffer and memory device including the same
    9.
    发明授权
    Input buffer and memory device including the same 有权
    输入缓冲器和包含相同的存储器件

    公开(公告)号：US09214202B2

    公开(公告)日：2015-12-15

    申请号：US14644339

    申请日：2015-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yong Shim ,  Seung-Jun Bae ,  Won-Joo Yun

    IPC: G11C16/04 ,  G11C7/10

    CPC classification number: G11C7/1084 ,  G11C7/1054

    Abstract: An input buffer includes a first buffer, a feedback circuit and a second buffer circuit. The feedback circuit includes a feedback resistor and a feedback inverter. The first buffer may be configured to output an amplification signal to an output node of the first buffer based on an input signal. The feedback circuit connected to the output node of the first buffer may be configured to control the amplification signal. The second buffer circuit may be configured to output a buffer output signal by buffering the amplification signal. The feedback resistor may receive the amplification signal from the output node of the first buffer and provide a feedback signal to a feedback node. The feedback inverter is connected between the feedback node and the output node. The feedback inverter may be configured to control the amplification signal based on the feedback signal.

    Abstract translation: 输入缓冲器包括第一缓冲器，反馈电路和第二缓冲电路。 反馈电路包括反馈电阻和反馈反馈器。 第一缓冲器可以被配置为基于输入信号将放大信号输出到第一缓冲器的输出节点。 连接到第一缓冲器的输出节点的反馈电路可以被配置为控制放大信号。 第二缓冲电路可以被配置为通过缓冲放大信号来输出缓冲器输出信号。 反馈电阻器可以从第一缓冲器的输出节点接收放大信号，并向反馈节点提供反馈信号。 反馈逆变器连接在反馈节点和输出节点之间。 反馈反相器可以被配置为基于反馈信号来控制放大信号。

    Duty cycle corrector and systems including the same
    10.
    发明授权
    Duty cycle corrector and systems including the same 有权
    占空比校正器和系统包括相同

    公开(公告)号：US09053774B2

    公开(公告)日：2015-06-09

    申请号：US14066193

    申请日：2013-10-29

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ho-Seok Seol ,  Seung-Jun Bae ,  Ho-Sung Song

    IPC: G11C7/00 ,  G11C8/18 ,  H03K5/156 ,  G11C29/02

    CPC classification number: G11C8/18 ,  G11C29/023 ,  G11C29/028 ,  H03K5/1565

    Abstract: A duty cycle corrector includes a sensing unit, a pad unit, a fuse unit, and a driver unit. The sensing unit generates at least one sensing signal based on the sensed duty cycle ratio of an output signal. The pad unit outputs at least one decision signal based on the at least one sensing signal. The fuse unit generates a duty cycle control signal based on at least one received fuse control signal. The driver unit adjusts a duty cycle ratio of an input signal to generate the output signal based on the duty cycle control signal. The driver unit adjusts the duty cycle ratio of the input signal by adjusting a pull-up strength or a pull-down strength of the input signal based on the duty cycle control signal.

    Abstract translation: 占空比校正器包括感测单元，衬垫单元，保险丝单元和驱动单元。 感测单元基于感测到的输出信号的占空比来产生至少一个感测信号。 垫单元基于至少一个感测信号输出至少一个判定信号。 熔丝单元基于至少一个接收的熔丝控制信号产生占空比控制信号。 驱动单元根据占空比控制信号来调整输入信号的占空比，生成输出信号。 驱动器单元通过基于占空比控制信号调整输入信号的上拉强度或下拉强度来调节输入信号的占空比。

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