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    Power amplifier having depletion mode high electron mobility transistor
    3.
    发明授权
    Power amplifier having depletion mode high electron mobility transistor 有权
    具有耗尽型高电子迁移率晶体管的功率放大器

    公开(公告)号：US08294521B2

    公开(公告)日：2012-10-23

    申请号：US12855055

    申请日：2010-08-12

    申请人： Dong Min Kang ,  Hong Gu Ji ,  Hokyun Ahn ,  Jong-Won Lim ,  Woojin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Hae Cheon Kim

    发明人： Dong Min Kang ,  Hong Gu Ji ,  Hokyun Ahn ,  Jong-Won Lim ,  Woojin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Hae Cheon Kim

    IPC分类号： H03F3/04

    CPC分类号： H03F3/24 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222

    摘要： Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.

    摘要翻译： 提供了一种功率放大器，包括：耗尽型高电子迁移率晶体管（D模式HEMT），被配置为放大输入到栅极端子的信号，并通过漏极端子输出放大的信号; 输入匹配电路，被配置为使所述栅极端子串联接地; 以及连接在漏极端子和地之间的DC偏置电路。 通过上述配置，HEMT可以仅由单个DC偏置电路偏压而没有任何偏置装置来提供负电压。 此外，可以通过并联电感器和扼流电感器在各种工作频带中提供优异的匹配特性。

    Method of manufacturing a field-effect transistor
    4.
    发明授权
    Method of manufacturing a field-effect transistor 有权
    制造场效应晶体管的方法

    公开(公告)号：US08586462B2

    公开(公告)日：2013-11-19

    申请号：US13307069

    申请日：2011-11-30

    申请人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

    发明人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

    IPC分类号： H01L29/808 ,  H01L21/283

    CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

    摘要： Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

    摘要翻译： 公开了一种制造场效晶体管的方法。 所公开的方法包括：提供半导体衬底; 在半导体衬底的一侧上形成源极欧姆金属层; 在所述半导体衬底的另一侧上形成漏极欧姆金属层; 在所述源欧姆金属层和所述漏极欧姆金属层之间形成栅电极，在所述半导体衬底的上部; 在包括源欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上形成绝缘膜; 以及在绝缘膜的上部形成多个场电极，其中各个场电极下方的绝缘膜具有不同的厚度。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20120146107A1

    公开(公告)日：2012-06-14

    申请号：US13274367

    申请日：2011-10-17

    申请人： Jong-Won LIM ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

    发明人： Jong-Won LIM ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

    IPC分类号： H01L29/772 ,  H01L21/28

    CPC分类号： H01L29/42376 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

    摘要： Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

    摘要翻译： 公开了一种半导体器件及其制造方法。 在根据本公开的示例性实施例的半导体器件中，在具有诸如AlGaN / GaN的异质结结构的衬底上形成源电极，漏电极，场板电极和栅电极时， 由与栅电极相同的金属制成的场板电极形成在位于栅电极的头部下方的第二支撑部分的侧表面上，以防止栅电极塌陷并改善高频和高电压 半导体器件的特性。

    FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF
    6.
    发明申请
    FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF 有权
    场效应晶体管及其制造方法

    公开(公告)号：US20120153361A1

    公开(公告)日：2012-06-21

    申请号：US13307069

    申请日：2011-11-30

    申请人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

    发明人： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

    IPC分类号： H01L21/283 ,  H01L29/808

    CPC分类号： H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

    摘要： Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

    摘要翻译： 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括：半导体衬底; 源极欧姆金属层，形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极，位于所述半导体衬底的上部; 形成在包括源极欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极，其中，各个场电极下方的绝缘膜具有不同的厚度。

    Semiconductor device with T-gate electrode
    8.
    发明授权
    Semiconductor device with T-gate electrode 失效
    具有T型栅电极的半导体器件

    公开(公告)号：US07973368B2

    公开(公告)日：2011-07-05

    申请号：US12122982

    申请日：2008-05-19

    申请人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

    发明人： Jong Won Lim ,  Ho Kyun Ahn ,  Hong Gu Ji ,  Woo Jin Chang ,  Jae Kyoung Mun ,  Hae Cheon Kim ,  Hyun Kyu Yu

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L29/778 ,  H01L29/20 ,  H01L29/42316 ,  H01L29/66462

    摘要： Provided are a semiconductor device with a T-gate electrode capable of improving stability and a high frequency characteristic of the semiconductor device by reducing source resistance, parasitic capacitance, and gate resistance and a method of fabricating the same. In the semiconductor device, in order to form source and drain electrodes and the T-gate electrode on a substrate, first and second protective layers constructed with silicon oxide layers or silicon nitride layers are formed on sides of a supporting part under a head part of the T-gate electrode, and the second protective layer constructed with a silicon oxide layer or silicon nitride layer is formed on sides of the source and drain electrodes. Accordingly, it is possible to protect an activated region of the semiconductor device and reduce gate-drain parasitic capacitance and gate-source parasitic capacitance.

    摘要翻译： 提供一种具有T栅电极的半导体器件及其制造方法，该半导体器件能够通过降低源极电阻，寄生电容和栅极电阻来提高半导体器件的稳定性和高频特性。 在半导体器件中，为了在衬底上形成源电极和漏电极以及T栅电极，在氧化硅层或氮化硅层构成的第一和第二保护层形成在支撑部分的头部 在栅电极和漏电极的侧面上形成T形栅电极和由氧化硅层或氮化硅层构成的第二保护层。 因此，可以保护半导体器件的激活区域并减小栅极 - 漏极寄生电容和栅极 - 源极寄生电容。

    Transistor of semiconductor device and method of fabricating the same
    9.
    发明授权
    Transistor of semiconductor device and method of fabricating the same 有权
    半导体器件的晶体管及其制造方法

    公开(公告)号：US07871874B2

    公开(公告)日：2011-01-18

    申请号：US12396614

    申请日：2009-03-03

    申请人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

    发明人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66462 ,  H01L29/7785

    摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

    摘要翻译： 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。

    Transistor or semiconductor device comprising ohmic contact in an epitaxy substrate
    10.
    发明授权
    Transistor or semiconductor device comprising ohmic contact in an epitaxy substrate 有权
    在外延衬底中包括欧姆接触的晶体管或半导体器件

    公开(公告)号：US07518166B2

    公开(公告)日：2009-04-14

    申请号：US11179971

    申请日：2005-07-12

    申请人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

    发明人： Jae Kyoung Mun ,  Jong Won Lim ,  Woo Jin Chang ,  Hong Gu Ji ,  Ho Kyun Ahn ,  Hae Cheon Kim

    IPC分类号： H01L29/74

    CPC分类号： H01L29/66462 ,  H01L29/7785

    摘要： Provided are a transistor of a semiconductor device and method of fabricating the same. The transistor includes: an epitaxy substrate disposed on a semi-insulating substrate and having a buffer layer, a first Si planar doping layer, a first conductive layer, a second Si planar doping layer, and a second conductive layer, which are sequentially stacked, the second Si planar doping layer having a doping concentration different from that of the first Si planar doping layer; a source electrode and a drain electrode diffusing into the first Si planar doping layer to a predetermined depth and disposed on both sides of the second conductive layer to form an ohmic contact; and a gate electrode disposed on the second conductive layer between the source and drain electrodes and being in contact with the second conductive layer. In this structure, both isolation and switching speed of the transistor can be increased. Also, the maximum voltage limit applied to the transistor is increased due to increases in gate turn-on voltage and threshold voltage and a reduction in parallel conduction element. As a result, the power handling capability of the transistor can be improved, thus improving a high-power low-distortion characteristic and an isolation characteristic.

    摘要翻译： 提供半导体器件的晶体管及其制造方法。 晶体管包括：设置在半绝缘衬底上并具有缓冲层的外延衬底，第一Si平面掺杂层，第一导电层，第二Si平面掺杂层和第二导电层， 所述第二Si平面掺杂层具有与所述第一Si平面掺杂层的掺杂浓度不同的掺杂浓度; 源极电极和漏电极，其扩散到所述第一Si平面掺杂层中至预定深度并且设置在所述第二导电层的两侧以形成欧姆接触; 以及设置在所述源极和漏极之间的所述第二导电层上并与所述第二导电层接触的栅电极。 在这种结构中，可以提高晶体管的隔离和开关速度。 此外，施加到晶体管的最大电压限制由于栅极导通电压和阈值电压的增加以及并联导通元件的减小而增加。 结果，可以提高晶体管的功率处理能力，从而提高高功率低失真特性和隔离特性。