公开(公告)号：US20150206814A1

公开(公告)日：2015-07-23

申请号：US14290217

申请日：2014-05-29

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L23/14 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/26533 ,  H01L21/486 ,  H01L29/762 ,  H01L29/7834 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

Abstract translation: 提供一种用于安装半导体器件的层结构的制造方法，其包括以下步骤：提供基材，其中所述基材具有导电层，所述导电层具有第一表面，所述第一表面具有多个第一导电元件和相对的第二表面 具有多个第二导电元件，以及第一密封剂，其形成在所述导电层的第一表面上，用于封装所述第一导电元件; 部分去除所述导电层以形成电连接所述第一导电元件和所述第二导电元件的电路层; 以及在所述第一密封剂的底表面上形成用于封装所述电路层和所述第二导电元件的第二密封剂，从而降低制造难度并提高产品产率。

公开(公告)号：US10396021B2

公开(公告)日：2019-08-27

申请号：US15950734

申请日：2018-04-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L21/48 ,  H01L29/78 ,  H01L21/265 ,  H01L23/498 ,  H01L29/762

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

公开(公告)号：US09589841B2

公开(公告)日：2017-03-07

申请号：US14981364

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Yi-Feng Chang

IPC: H01L23/31 ,  H01L23/498 ,  H01L21/56 ,  H01L21/78 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01L21/78 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Abstract translation: 提供了一种制造电子封装件的方法，包括以下步骤：提供至少一种包装结构，其中该封装结构具有包含相对的第一和第二侧的封装基板，设置在该封装基板的第一面上的电子元件，以及 形成在所述封装基板的第一面上的多个导体; 用绝缘层封装封装结构，其中绝缘层覆盖封装衬底; 以及在所述绝缘层上形成RDL（再分配层）结构，其中所述RDL结构电连接到所述导体。 因此，绝缘层的面积不需要对应于封装基板的面积，因此可以根据实际需要减小封装基板的面积，以减小电子封装的宽度。

公开(公告)号：US20160240466A1

公开(公告)日：2016-08-18

申请号：US14981364

申请日：2015-12-28

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Yan-Heng Chen ,  Yi-Feng Chang

IPC: H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L21/48

CPC classification number: H01L21/78 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5389 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A method for fabricating an electronic package is provided, including the steps of: providing at least a packaging structure, wherein the packaging structure has a packaging substrate having opposite first and second sides, an electronic element disposed on the first side of the packaging substrate and a plurality of conductors formed on the first side of the packaging substrate; encapsulating the packaging structure with an insulating layer, wherein the insulating layer covers the packaging substrate; and forming an RDL (Redistribution Layer) structure on the insulating layer, wherein the RDL structure is electrically connected to the conductors. Therefore, the area of the insulating layer is not required to correspond to the area of the packaging substrate, thus allowing the area of the packaging substrate to be reduced according to the practical need so as to reduce the width of the electronic package.

Abstract translation: 提供了一种制造电子封装件的方法，包括以下步骤：提供至少一种包装结构，其中该封装结构具有包含相对的第一和第二侧的封装基板，设置在该封装基板的第一面上的电子元件，以及 形成在所述封装基板的第一面上的多个导体; 用绝缘层封装封装结构，其中绝缘层覆盖封装衬底; 以及在所述绝缘层上形成RDL（再分配层）结构，其中所述RDL结构电连接到所述导体。 因此，绝缘层的面积不需要对应于封装基板的面积，因此可以根据实际需要减小封装基板的面积，以减小电子封装的宽度。

公开(公告)号：US20150044821A1

公开(公告)日：2015-02-12

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56 ,  H01L25/065

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.

Abstract translation: 提供了一种多芯片堆叠结构及其制造方法。 制造多芯片堆叠结构的方法包括通过使用阶梯状方式将包括多个第一芯片的第一芯片组布置在芯片载体上，将第二芯片设置在第一芯片组的顶部上的第一芯片上， 通过接合线将第一芯片组和第二芯片电连接到芯片载体上，使用薄膜覆盖线（FOW）来在第一芯片和第二芯片之间设置绝缘膜，其中绝缘膜覆盖部分 在第一组的顶部和第二芯片的至少一部分上的第一芯片的接合线的端部，并且通过接合线将第三芯片电连接到芯片载体，从而防止直接布置在第一芯片上 第二芯片的平面尺寸远远小于现有技术中的第一芯片的平面尺寸，这增加了整个结构的高度，并且难以增加布线接合。

公开(公告)号：US20180233442A1

公开(公告)日：2018-08-16

申请号：US15950734

申请日：2018-04-11

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L23/498 ,  H01L21/265 ,  H01L29/78 ,  H01L29/762 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/26533 ,  H01L21/486 ,  H01L29/762 ,  H01L29/7834 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

公开(公告)号：US20180211925A1

公开(公告)日：2018-07-26

申请号：US15492394

申请日：2017-04-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/552 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L21/48 ,  H01L21/78 ,  H01L21/52 ,  H01L25/00

CPC classification number: H01L23/552 ,  H01L21/4817 ,  H01L21/52 ,  H01L21/561 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3128 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/81 ,  H01L2924/014

Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US10236261B2

公开(公告)日：2019-03-19

申请号：US15492394

申请日：2017-04-20

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Lung-Yuan Wang

IPC: H01L23/552 ,  H01L21/48 ,  H01L21/56 ,  H01L21/52 ,  H01L23/31 ,  H01L23/16 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: An electronic package is provided, which includes: a substrate; an electronic component and a shielding member disposed on the substrate; an encapsulant formed on the substrate and encapsulating the electronic component and the shielding member; and a metal layer formed on the encapsulant and electrically connected to the shielding member. A portion of a surface of the shielding member is exposed from a side surface of the encapsulant and in contact with the metal layer. As such, the width of the shielding member can be reduced so as to reduce the amount of solder paste used for bonding the shielding member to the substrate, thereby overcoming the conventional drawback of poor solder distribution. The present disclosure further provides a method for fabricating the electronic package.

公开(公告)号：US09972564B2

公开(公告)日：2018-05-15

申请号：US14290217

申请日：2014-05-29

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Fang-Lin Tsai ,  Yi-Feng Chang ,  Cheng-Jen Liu ,  Yi-Min Fu ,  Hung-Chi Chen

IPC: H01L23/498 ,  H01L29/78 ,  H01L21/265 ,  H01L29/762 ,  H01L21/48

CPC classification number: H01L23/49827 ,  H01L21/26533 ,  H01L21/486 ,  H01L29/762 ,  H01L29/7834 ,  H01L2224/16225 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A fabrication method of a layer structure for mounting a semiconductor device is provided, which includes the steps of: providing a base material, wherein the base material has a conductive layer having a first surface having a plurality of first conductive elements and an opposite second surface having a plurality of second conductive elements, and a first encapsulant formed on the first surface of the conductive layer for encapsulating the first conductive elements; partially removing the conductive layer to form a circuit layer that electrically connects the first conductive elements and the second conductive elements; and forming a second encapsulant on a bottom surface of the first encapsulant for encapsulating the circuit layer and the second conductive elements, thus reducing the fabrication difficulty and increasing the product yield.

公开(公告)号：US09754927B2

公开(公告)日：2017-09-05

申请号：US14524166

申请日：2014-10-27

Applicant: Siliconware Precision Industries Co., Ltd.

Inventor： Chung-Lun Liu ,  Jung-Pin Huang ,  Yi-Feng Chang ,  Chin-Huang Chang

IPC: H01L29/15 ,  H01L25/00 ,  H01L23/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L25/50 ,  H01L21/56 ,  H01L23/3107 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/858 ,  H01L2224/8592 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/15321 ,  H01L2924/15323 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A multi-chip stack structure and a method for fabricating the same are provided. The method for fabricating a multi-chip stack structure includes disposing a first chip group comprising a plurality of first chips on a chip carrier by using a step-like manner, disposing a second chip on the first chip on top of the first chip group, electrically connecting the first chip group and the second chip to the chip carrier through bonding wires, using film over wire (FOW) to stack a third chip on the first and the second chips with an insulative film provided therebetween, wherein the insulative film covers part of the ends of the bonding wires of the first chip on the top of the first group and at least part of the second chip, and electrically connecting the third chip to the chip carrier through bonding wires, thereby preventing directly disposing on a first chip a second chip having a planar size far smaller than that of the first chip as in the prior art that increases height of the entire structure and increases the wiring bonding difficultly.