公开(公告)号：US11721738B2

公开(公告)日：2023-08-08

申请号：US17197188

申请日：2021-03-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L23/528 ,  H01L29/417 ,  H01L29/10

CPC classification number: H01L29/4238 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/7835 ,  H01L23/528 ,  H01L29/1045 ,  H01L29/41758 ,  H01L29/42368

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US11189721B2

公开(公告)日：2021-11-30

申请号：US16995133

申请日：2020-08-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08 ,  H01L21/8234 ,  H01L29/40 ,  H01L29/06 ,  H01L29/423 ,  H01L21/225 ,  H01L21/283 ,  H01L21/324 ,  H01L29/51

Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

公开(公告)号：US10957774B2

公开(公告)日：2021-03-23

申请号：US16127281

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L23/528 ,  H01L29/417 ,  H01L29/10

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US09076863B2

公开(公告)日：2015-07-07

申请号：US13944864

申请日：2013-07-17

Applicant: Texas Instruments Incorporated

Inventor： Takehito Tamura ,  Binghua Hu ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L21/762 ,  H01L21/76229 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/06 ,  H01L29/0619 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

Abstract: The density of a transistor array is increased by forming one or more deep trench isolation structures in a semiconductor material. The deep trench isolation structures laterally surround the transistors in the array. The deep trench isolation structures limit the lateral diffusion of dopants and the lateral movement of charge carriers.

Abstract translation: 通过在半导体材料中形成一个或多个深沟槽隔离结构来增加晶体管阵列的密度。 深沟槽隔离结构横向围绕阵列中的晶体管。 深沟槽隔离结构限制了掺杂剂的横向扩散和载流子的横向移动。

公开(公告)号：US10608075B2

公开(公告)日：2020-03-31

申请号：US16240194

申请日：2019-01-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

公开(公告)号：US10177215B1

公开(公告)日：2019-01-08

申请号：US15793690

申请日：2017-10-25

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L29/94

Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.

公开(公告)号：US20190006514A1

公开(公告)日：2019-01-03

申请号：US16127281

申请日：2018-09-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/49 ,  H01L29/08 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L21/22 ,  H01L23/528 ,  H01L29/423

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US20180190814A1

公开(公告)日：2018-07-05

申请号：US15394636

申请日：2016-12-29

Applicant: Texas Instruments Incorporated

Inventor： Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/49 ,  H01L29/06 ,  H01L29/66 ,  H01L21/22 ,  H01L21/28

CPC classification number: H01L29/7816 ,  H01L21/22 ,  H01L21/28035 ,  H01L23/528 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1033 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/66681

Abstract: An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

公开(公告)号：US09240465B2

公开(公告)日：2016-01-19

申请号：US14821085

申请日：2015-08-07

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06 ,  H01L21/265 ,  H01L21/324 ,  H01L21/225 ,  H01L29/78 ,  H01L29/417

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

公开(公告)号：US09136368B2

公开(公告)日：2015-09-15

申请号：US14044909

申请日：2013-10-03

Applicant: Texas Instruments Incorporated

Inventor： Marie Denison ,  Sameer Pendharkar ,  Guru Mathur

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L29/78 ,  H01L29/66 ,  H01L29/10 ,  H01L29/08

CPC classification number: H01L29/66712 ,  H01L21/225 ,  H01L21/26513 ,  H01L21/324 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/42368 ,  H01L29/66674 ,  H01L29/66734 ,  H01L29/7801 ,  H01L29/7809 ,  H01L29/7813

Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.

Abstract translation: 半导体器件具有深沟槽结构的垂直漏极扩展MOS晶体管，以限定垂直漂移区域和至少一个垂直漏极接触区域，其通过深沟槽结构的至少一个实例与垂直漂移区域分离。 将掺杂剂注入到垂直漏极接触区域中，并且半导体器件被退火，使得注入的掺杂剂在深沟槽结构的底部附近扩散。 垂直漏极接触区域在中间深沟槽结构的底部处与邻近的垂直漂移区域电接触。 至少一个栅极，主体区域和源极区域形成在半导体器件的衬底的顶表面处或附近的漂移区域上方。 深沟槽结构被间隔开以形成漂移区域的RESURF区域。