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    Image processing accelerator
    2.
    发明授权
    Image processing accelerator 有权

    公开(公告)号：US10747692B2

    公开(公告)日：2020-08-18

    申请号：US16234508

    申请日：2018-12-27

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Mihir Mody ,  Niraj Nandan ,  Hetul Sanghvi ,  Brian Chae ,  Rajasekhar Reddy Allu ,  Jason A. T. Jones ,  Anthony Lell ,  Anish Reghunath

    IPC: G06F13/16 ,  G06T1/20 ,  H04N5/765 ,  G06F13/28

    Abstract: A processing accelerator includes a shared memory, and a stream accelerator, a memory-to-memory accelerator, and a common DMA controller coupled to the shared memory. The stream accelerator is configured to process a real-time data stream, and to store stream accelerator output data generated by processing the real-time data stream in the shared memory. The memory-to-memory accelerator is configured to retrieve input data from the shared memory, to process the input data, and to store, in the shared memory, memory-to-memory accelerator output data generated by processing the input data. The common DMA controller is configured to retrieve stream accelerator output data from the shared memory and transfer the stream accelerator output data to memory external to the processing accelerator; and to retrieve the memory-to-memory accelerator output data from the shared memory and transfer the memory-to-memory accelerator output data to memory external to the processing accelerator.

    PCIe peripheral sharing
    5.
    发明授权
    PCIe peripheral sharing 有权

    公开(公告)号：US11609866B2

    公开(公告)日：2023-03-21

    申请号：US17073925

    申请日：2020-10-19

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Sriramakrishnan Govindarajan ,  Kishon Vijay Abraham Israel Vijayponraj ,  Mihir Narendra Mody ,  Jason A. T. Jones

    IPC: G06F13/16 ,  G06F13/42 ,  G06F12/10

    Abstract: A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.

    Multichannel memory arbitration and interleaving scheme
    6.
    发明授权
    Multichannel memory arbitration and interleaving scheme 有权

    公开(公告)号：US11960416B2

    公开(公告)日：2024-04-16

    申请号：US17558278

    申请日：2021-12-21

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Daniel Brad Wu ,  Abhishek Shankar ,  Mihir Narendra Mody ,  Gregory Raymond Shurtz ,  Jason A. T. Jones ,  Hemant Vijay Kumar Hariyani

    IPC: G06F13/16

    CPC classification number: G06F13/1647

    Abstract: Techniques including a memory controller with a set of memory channel queues, wherein memory channel queues of the set of memory channel queues correspond to memory channels to access a set of memory modules, a first arbitration module, and a second arbitration module. The memory controller is configured to receive a first memory request from the peripheral and place one or more portions of the first memory request in the memory channel queues of the set of memory channel queues. The first arbitration module is configured to determine an arbitration algorithm, select a first memory channel queue based on the arbitration algorithm, present the one or more portions of the first memory request in the selected first memory channel queue to the second arbitration module, and output the presented one or more portions of the first memory request based on a selection by the second arbitration module.

    Machine learning model with watermarked weights
    8.
    发明授权
    Machine learning model with watermarked weights 有权

    公开(公告)号：US11163861B2

    公开(公告)日：2021-11-02

    申请号：US16188560

    申请日：2018-11-13

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Deepak Kumar Poddar ,  Mihir Mody ,  Veeramanikandan Raju ,  Jason A. T. Jones

    IPC: G06F21/00 ,  G06F21/16 ,  G06N3/04 ,  G06N20/00 ,  G06F21/12

    Abstract: In some examples, a system includes storage storing a machine learning model, wherein the machine learning model comprises a plurality of layers comprising multiple weights. The system also includes a processing unit coupled to the storage and operable to group the weights in each layer into a plurality of partitions; determine a number of least significant bits to be used for watermarking in each of the plurality of partitions; insert one or more watermark bits into the determined least significant bits for each of the plurality of partitions; and scramble one or more of the weight bits to produce watermarked and scrambled weights. The system also includes an output device to provide the watermarked and scrambled weights to another device.

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